Journal of Circuits, Systems and Computers

Modern wireless communication poses the requirements of fast settling time, small channel width, and low phase noise to frequency synthesizer. ΣΔ fractional-N frequency synthesizer is widely adopted due to its excellent characteristics in these aspects. This paper presents a number of system issues and design considerations/tradeoffs which are involved in the design of such a frequency synthesizer from the system point of view. These considerations include selection of loop parameters, choice of key building blocks, and critical system performance issues like spurious tones, quantization noise, in-band phase noise, out-of-band phase noise, and frequency accuracy/resolution. Finally, the future possibilities are briefly analyzed.

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15–30% of the total power dissipation when compared to Dynamic Current mode logic.

This paper presents a novel design procedure for class DE amplifier. And design curves of class DE amplifier with switch on resistance as functions of output Q, duty ratio, and load resistance are clarified. The feature of the proposed design procedure is that the waveform equations are never required. The design procedure requires only circuit equations and the design specifications. When circuit equations are derived, the other procedures for computations of design values are carried out with aid of computer. Therefore, it is possible to design class DE amplifier at any conditions, namely, at any output Q, any duty ratio, any switch on resistance and so on. By carrying out the circuit experiments, we denote that the experimental results agree with the calculation results quantitatively, and show the validity of the proposed design procedure.

A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V V_DD and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 × 8 × 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 μm process and the power consumption can be further reduced using the more downsized technology designs.

An automated circuit analysis tool called SPICESoft, the main objective of which is to help designers in sensitivity computation and circuit analysis is presented. Three main features of SPICESoft are described, namely Sensitivity Analysis, Circuit Performance Analysis, and Inverse Circuit Performance Analysis. A new methodology called Binary Differential Expansion used for data interpolation is also described in this paper. The relationship between device and process parameters is covered. The simulation results obtained using the proposed automated tool are compared with those of conventional computation.

In this paper, we present a unique low power decimation filter architecture for RF wireless applications. To implement the low power decimation filter, we considered low power design techniques such as multi-rate, multi-stage signal processing, proper selection of decimation factor, one multiplier realization of 1/3-band filters, and poly-phase 1/2-band filters. We have designed three conventional decimation filter architectures using a single-stage FIR filter, a three-stage FIR filter, and a three-stage half-band FIR filter. Compared to the 55-tap comb-FIR filter architecture, the proposed decimation filter has only 13 taps, and requires 76% less hardware and consumes 64% less power.

For the sake of reducing the hardware cost of multiple RF chains and the complexity for spatial multiplexing systems, in this paper a novel low-complexity transmit antenna selection criterion is proposed for V-BLAST system with MMSE OSIC detection. Based on MMSE extension of V-BLAST with sorted QR decomposition, an intuitional performance analysis of each sub-stream for MMSE V-BLAST transmission is done, and a new solution to the transmit antenna selection problem is suggested. Unlike most of the existing works, the proposed algorithm synthetically considers the impacts of detection order, interference cancellation, and noise amplification. Theoretical analysis and simulation results show that the proposed algorithm achieves well both in outage capacity and in symbol error rate performance with low computational complexity.

This note proposes a systematic method to optimizing dynamic output feedback controller for continuous-time hybrid systems in the Piecewise Affine (PWA) form. In this note, design of the dynamic output feedback controller is shown in the frame of L₂ gain synthesis for PWA systems. Matrix inequalities derived from dynamic output feedback controller is not usually linear. Using a congruence transformation, the nonlinear matrix inequalities are mapped into linear matrix inequalities, whose solutions are quite feasible using commercially available software. The proposed techniques satisfy features such as: globally quadratic stability, continuity of control signal, and tracking a reference input. A numerical example is included to demonstrate the applicability and effectiveness of the proposed technique.

This paper presents a simple and systematic approach to the design of an H_∞ loop-shaping controller for a boost converter operating in continuous conduction mode. Using an averaged linear model of the converter, a robust controller is developed, guaranteeing stability, and the desired closed-loop dynamic response. A controller exists if and only if the unique stabilizing solutions to two algebric Riccati equations are positive definite and the spectral radius of their product is less than . Under these conditions, a compact control structure is obtained and the controller is parameterized. The main contribution of the tuning rules is that the controller parameters can be obtained using one design parameter which reflects the trade-off between stability robustness and time domain performance. Various aspects of the design, including the associated practical problems and the proposed solutions, are detailed. Simulation results are presented to illustrate the design procedure.

This paper links the two-dimension-spread-spectrum-system source separation problem to the trilinear model, which is an analysis tool rooted in psychometrics and chemometrics. Exploiting this link, it derives a blind source separation algorithm. The proposed algorithm capitalizes on time-domain spread, frequency-domain spread and temporal diversity-combining. The simulation results reveal that the performance of the blind source separation algorithm for two-dimension spread spectrum system is very close to nonblind minimum mean-squared error method, and this algorithm works well for small sample size. The blind source separation algorithm does not require channel fading information and spread codes, so it has blind and robust characteristics.

The design of a MEMS ultrasonic sensor has been presented that exploits the Single Bubble Sonoluminescence (SBSL) phenomenon to realize an energy transduction mechanism from acoustical to electrical domain. In the developed scheme, highly stable laser like short duration light pulses are emitted when ultrasound waves strike a thermally generated microbubble stabilized in a confined volume of 1% xenon-enriched water. The emitted light pulses are detected by an integrated profiled silicon type photodetector to generate ultrastable 100 picoseconds duration current pulses per acoustical cycle. The sensor exhibits energy amplification during the transduction process itself that is not achievable by conventional types of MEMS or non-MEMS acoustical sensors. The cylindrical sensor geometry is 650 μm in diameter and 300 μm in height and is designed to have a sensitivity of 5.56 mA/atm/cycle. The sensor can be used in applications where detection of high pressure ultrasound waves is necessary or as an ultrastable very short duration current pulse generator for use in tissue and nerve repair or microsurgery.

We introduce a recovery algorithm for low-density parity-check codes that provides substantial coding gain over the conventional method. Concisely, it consists of an inference procedure based on successive decoding rounds using different subsets of bit nodes from the bipartite graph representing the code. The technique also sheds light on certain characteristics of the sum–product algorithm and effectively copes with the problems of trapping sets, cycles, and other anomalies that adversely affect the performance LDPC codes.