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This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO₂ quantum dots. The work performed here builds off previous works performed with Si/SiO₂ dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

This paper presents the experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO₂ and Ge/GeO₂ quantum dots. The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge quantum dot layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow the reduction of FET count in logic block in microprocessors.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) $n$-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO₂ quantum dots. The work performed here builds off previous works performed with Si/SiO₂ dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

This paper presents the experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO₂ and Ge/GeO₂ quantum dots. The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge quantum dot layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow the reduction of FET count in logic block in microprocessors.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) n-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.