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A comprehensive SPICE model is developed for single photon avalanche diodes (SPADs). The model simulates both the static and dynamic behaviors of SPADs. Parameters of the model were extracted form experimental data obtained from SPADs designed and fabricated in a standard 0.5μm CMOS process. In this model, the resistive behavior of the device was modeled with an exponential function. Moreover, the device simulated response to incident optical power stimulation is modeled. Experimentally extracted parameters were incorporated into the model, and simulation results agreed with the experimental data.

A macromodel of silicon-on-insulator (SOI) four-gate transistor (G⁴FET) is presented in this paper to aid circuit designers to explore innovative applications circuit with this multi-gate transistor. A number of works based on analytical solution, numerical simulation and experimental results of G⁴FET have been previously reported. However, designing new interesting circuits with G⁴FETs requires a SPICE model that will work sufficiently well throughout the desired operating regions. Although it is theoretically possible to solve coupled non-linear differential equations to explore different operating conditions, this will take an excessive amount of time making it unsuitable for useful circuit design. Therefore, a macromodel approach is adopted in this work to provide a reasonably fast and accurate circuit simulation. G⁴FET combines the functionality of MOSFET and JFET devices which already have robust, fast and reliable SPICE models. A macromodel approach which is capable of combining these existing models including the interactions between multiple gates will be beneficial for any circuit designer. The feasibility of the macromodel is justified by simulating several analog and digital circuits and comparing against available experimental results.

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node.

TeraFET arrays operating in plasmonic regimes could support the transition from 5G to 6G communication if the constituent TeraFETs operate in synchrony. Such arrays are plasmonic crystals supporting Bloch-like waves of electron density oscillations. The key issues are breaking symmetry and maintaining appropriate boundary conditions between the unit cells. The symmetry must be broken to choose the response polarity to detect the direction of the plasmonic instability growth for generating THz oscillations. The coherence of plasma waves propagating in individual cells of the plasmonic crystal results in continuous waves in the entire structure. Using the narrow stripes at the unit cell edges (called plasmonic stubs) could maintain such coherence. Another advantage of TeraFET arrays is the reduced effects of parasitic contact resistance. This advantage is even more pronounced in ring plasmonic structures used for converting THz radiation into a magnetic field (giant inverse Faraday effect).

An automated circuit analysis tool called SPICESoft, the main objective of which is to help designers in sensitivity computation and circuit analysis is presented. Three main features of SPICESoft are described, namely Sensitivity Analysis, Circuit Performance Analysis, and Inverse Circuit Performance Analysis. A new methodology called Binary Differential Expansion used for data interpolation is also described in this paper. The relationship between device and process parameters is covered. The simulation results obtained using the proposed automated tool are compared with those of conventional computation.

Memristor had been first theorized nearly 40 years ago by Prof. Chua, as the fourth fundamental circuit element beside the three existing elements (Resistor, Capacitor and Inductor) but because no one has succeeded in building a memristor, it has long remained a theoretical element. Some months ago, Hewlett-Packard (hp) announced it created a memristor using a TiO₂/TiO_2-X structure. In this paper, the characteristics, structures and relations for the invented hp's memristor are briefly reviewed and then two general SPICE models for the charge-controlled and flux-controlled memristors are introduced for the first time. By adjusting the model parameters to the hp's memristor characteristics some circuit properties of the device are studied and then two important memristor applications as the memory cell in a nonvolatile-RAM structure and as the synapse in an artificial neural network are studied. By utilizing the introduced models and designing the appropriate circuits for two most important applications; a nonvolatile memory structure and a programmable logic gate, circuit simulations are done and the results are presented.

In this paper, we present a fast and simple SPICE-based technique for the performance characterization of BJT mixers. First, exploiting fundamental concepts, an AC equivalent circuit of a radio-frequency bipolar junction transistor mixer is derived. Second, this equivalent circuit is used to estimate the conversion gain, noise-figure, and nonlinearity characteristics of the mixer. The proposed technique has been validated using simulations on integrated and discrete transistor based mixer circuits.

This paper proposes and describes a charge amplifier-based interface electronics design methodology approach for piezoelectric polymer tactile sensors to be used for humanoid robot applications. The tactile sensor–consisting of a PVDF single sensor element–is illustrated, the electromechanical thickness mode behavior is modeled and a fabricated prototype is presented. The model allows associating the PVDF charge response to the effective load applied on the outer surface of the sensor. The model is also used as a key in the proposed design methodology to estimate the charge to be detected by the charge amplifier. A case study based on the design methodology approach is reported. The system (PVDF single taxel + interface electronics) is analyzed firstly, considering it as ideal and then when the nonidealities come into play. A charge amplifier-based interface electronics prototype is also presented. The implementation is used to validate the followed approach and then defining the design specs towards the dedicated IC design. Some experimental results are also reported.

Aggressive miniaturization has led to severe performance and signal integrity issues in copper-based interconnects in the nanometric regime. As a consequence, development of a proper analytical model for such interconnects is extremely important. In this work, an ABCD parameter matrix-based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper-based nanointerconnect systems. Using the proposed model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future integrated circuit technology nodes of 21 and 15 nm, respectively. Proposed model has been compared with SPICE and it is found that this model is almost 100% accurate as SPICE with respect to both the crosstalk delay as well as noise. Moreover, this model is as much as ~ 63 and ~ 155 times faster, respectively. From the crosstalk delay and noise analysis of unrepeated interconnects, it is observed that both delay and noise contribution will increase in scaled technology nodes. The same trend is observed also for the repeated interconnects. Also more number of repeaters and higher repeater sizes will be needed for delay minimization as we scale deeper. So as far as crosstalk induced effects are concerned, the copper interconnects will face a huge challenge to overcome in nanometer technology nodes.

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors.

This paper approximates the behavior of low-pass Bessel filter in fractional domain using the Interior search algorithm (ISA). A detailed analysis has been done with sensitivity analysis, W-plane stability and absolute percentage error (gain and cut-off frequency) to study the low-pass fractional order filter. The work focuses on the analysis and design of fractional filter with two cases. In the first case, the design and simulation of $(1+\alpha )$ order low-pass Bessel filter has been done using MATLAB for $\alpha$ value ranging from 0.1 to 0.9. SPICE simulation of 1.2, 1.5 and 1.9 order low-pass Bessel filter using fractional order capacitor of order $\alpha$ with Tow–Thomas biquad have been performed. In the second case, low-pass ($\alpha +\beta )$ order Bessel filter has been simulated and designed using MATLAB, where $\alpha$ and $\beta$ are two fractional order elements of a different order. SPICE simulation for different values of $\alpha$ and $\beta$ have been done using two fractional order capacitors of $\alpha$ and $\beta$ order with Tow–Thomas biquad.

This paper contributes to the understanding of memristor operation and its possible application fields through: (a) derivation of a complete mathematical model for the HP memristor which takes into consideration the inter-dependence between memristance, charge and flux along with the boundary and initial conditions of operation; (b) an introduction of detailed charge- and flux-controlled SPICE memristor models realizing the proposed mathematical memristor model; (c) The incorporation of the memristor model in the SPICE realization of a third-order chaotic system where a single HP memristor acts as the nonlinear part of the system. Simulation results are provided to validate the mathematical model and the synthesis and operation of the third-order chaotic system.

The memristor is a novel circuit element which is capable of maintaining an activity-dependent nonvolatile resistance and is therefore a candidate for use in next-generation storage and logic circuits. In this article, we present a model of the PEO-PANI memristor for use in the SPICE circuit simulation program which is especially suited to analog logic applications. Two variants are presented herein; accompanying each is a short description that explains any design decisions made, as well as elucidating on preferred simulation settings. It is shown that the model accurately replicates corresponding experimental results found in the literature. Simple simulations are used to show the suitability of each variant to specific experimental usage. Appendices contain verbatim implementations of the SPICE models.

Desktop Virtualization is an essential problem in cloud manufacturing to make full use of shared resources so as to meet the practical application requirements. In this paper, an efficient virtualization solution for desktop transferring is presented for sharing resources. Our strategy is not limited to transfer desktops between virtual machines (VMs), transmission between virtual and physical machines is also achieved. A three-layer systemic structure based on web environment is proposed in the study. We employ the application program library Libvirt and kernel-based virtual machine (KVM) technique to manage VMs with dynamic customization scheme, which gains better virtualization performance. Moreover, we present two different schemes for desktop graphics transferring. One is based on the transport protocol virtual network computing (VNC), and the other adopts the simple protocol for independent computing environment (SPICE), which both achieve more satisfactory results. The validity of our scheme is demonstrated on some experimental results and systemic qualitative evaluation is also provided.

A macromodel of silicon-on-insulator (SOI) four-gate transistor (G⁴FET) is presented in this paper to aid circuit designers to explore innovative applications circuit with this multi-gate transistor. A number of works based on analytical solution, numerical simulation and experimental results of G⁴FET have been previously reported. However, designing new interesting circuits with G⁴FETs requires a SPICE model that will work sufficiently well throughout the desired operating regions. Although it is theoretically possible to solve coupled non-linear differential equations to explore different operating conditions, this will take an excessive amount of time making it unsuitable for useful circuit design. Therefore, a macromodel approach is adopted in this work to provide a reasonably fast and accurate circuit simulation. G⁴FET combines the functionality of MOSFET and JFET devices which already have robust, fast and reliable SPICE models. A macromodel approach which is capable of combining these existing models including the interactions between multiple gates will be beneficial for any circuit designer. The feasibility of the macromodel is justified by simulating several analog and digital circuits and comparing against available experimental results.