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We present an overview of radiation effects in silicon-germanium heterojunction bipolar transistors (SiGe HBT). We begin by reviewing SiGe HBTs, and then examine the impact of ionizing radiation on both the dc and ac performance of SiGe HBTs, the circuit-level impact of radiation-induced changes in the transistors, followed by single-event phenomena in SiGe HBT circuits. While ionizing radiation degrades both the dc and ac properties of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. SiGe HBT technology thus offers many interesting possibilities for space-borne electronic systems.

We present design considerations for high speed high swing differential modulator drivers in SiGeBiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.

In this article is presented the new SON process, which key point lies in the transfer of the lattice continuity from a bulk Silicon substrate via a SiGe layer to the Silicon cap layer, both of these layers being obtained by epitaxy. The thin SiGe layer is next removed from underneath the Si cap in an isotropic plasma-assisted chemical dry-etching. The mono-crystalline Si cap layer resulting from this process lies on an air-gap, which gives the name (Silicon On Nothing) to the process. Depending on application, this air-gap may be refilled with a dielectric or with a gate material for double gate applications. In both cases, the thickness of the Si cap as well as that of the air-gap (filled by the dielectric for single gate applications) may be in the range of a few nanometers with a control in the range of the epitaxy process capability. In this article we present the SON process and its implementation to MOSFETs devices and circuits. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors, Gate All Around or multi-gate devices.

Energy efficient hetero-junction tunneling transistors in a simple "cross-point" configuration that utilizes top gates are analyzed for use at extremely scaled sub-10 nm gate-lengths. The active tunneling region comprises of a vertical p++/n+ heterojunction (for example formed at the cross point of p++SiGe/n+Si), where modulation of the energy-bands in the gated n+Si region with a top-gate is used to control the degree of band overlap and tunneling distance and hence current. The sub-threshold swing characteristic of these devices is shown to be potentially highly immune to extreme downscaling to 6 nm gate length allowing for an intact and efficient switching behavior to be retained. The extreme scalability and ultra-low voltage operation could make such cross-point devices useful for alternative applications and architectures that require ultimate energy efficiency.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.