Journal of Circuits, Systems and Computers

Side-channel attacks (SCAs) are powerful noninvasive attacks that can be used for leaking the secret key of integrated circuits (ICs). Numerous countermeasures were proposed to elevate the security level of ICs against SCAs. Unfortunately, it is quite inconvenient to predict the security levels of these countermeasures since no solid mathematical model exists in the literature. In this paper, neural network (NN)-based entropy is proposed to model the resilience of a system against SCAs. The NN-based entropy model well links the side-channel leakages and probabilities with the neurons and weights of NNs, respectively. In such a circumstance, the NN-based entropy can be used for modeling the robustness of countermeasures since a one-to-one relationship is established between the NN-based entropy and the measurement-to-disclose (MTD) enhancement ratio related with the countermeasures. As demonstrated in the result, the proposed NN-based entropy metric shows 100% consistency with the MTD enhancement ratio if multiple SCA countermeasures are employed into a system.

The aim of this research is to create a medical expert system based on Bayes theorem to diagnose level of disc hernia based on real foot force measurement signals obtained using sensors and implement the whole system on field programable gate array (FPGA). We have created a database of attributes based on recorded foot force values of 33 patients pre-diagnosed with herniated disc on levels L4/L5 or L5/S1 on the left or right side. The results obtained by software (Matlab) and hardware (FPGA simulation) are matching well, achieving high accuracy, which shows that VHDL implementation of Naïve Bayes theorem for disc hernia diagnostics is adequate. The output on FPGA is easy to understand for any user, as it is implemented as four-bit output where the position of bit value 1 indicates the level of disc herniation. The system is able to distinguish between the healthy subjects and subjects with disc herniation and is able to detect if improvement in stability is present after surgery or physical therapy. Our proposed measurement platform can be coupled with FPGA to create a portable and not expensive tool for real time signal acquisition, processing and decision support system in disc hernia diagnosis and post-surgical recovery.

A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites.

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ($G_m$-$C$)-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the $G_m$-$C$ filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order $G_m$-$C$ filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved $-$3dB cut-off frequency of 16.51MHz and 17.22MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33$\mu$s and 0.32$\mu$s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18$\mu$m CMOS process.

In the medical field, the clinical notes taken by the doctor, nurse, or medical practitioner are considered to be one of the most important medical documents. These documents hold information regarding the patient including the patient’s current condition, family history, disease, symptoms, medications, lab test reports, and other vital information. Despite these documents holding important information regarding the patients, they cannot be used as the data are unstructured. Organizing a huge amount of data without any mistakes is highly impossible for humans, so ignoring unstructured data is not advisable. Hence, to overcome this issue, the web scraping method is used to extract the clinical notes from the Medical Transcription (MT) samples which hold many transcripted clinical notes of various departments. In the proposed method, Natural Language Processing (NLP) is used to pre-process the data, and the variants of the Term Frequency-Inverse Document Frequency (TF-IDF)-based vector model are used for the feature selection, thus extracting the required data from the clinical notes. The performance measures including the accuracy, precision, recall and F1 score are used in the identification of disease, and the result obtained from the proposed system is compared with the best performing machine learning algorithms including the Logistic Regression, Multinomial Naive Bayes, Random Forest classifier and Linear SVC. The result obtained proves that the Random Forest Classifier obtained a higher accuracy of 90% when compared to the other algorithms.

The price of the product has a great impact on the market competitiveness of the product. The manager can adjust the operation strategy according to the cost information of the product, cut costs, adjust the market decision and make the product more competitive in the market. Therefore, the research of product costing method has a very important significance. Considering that the physical resources in the processing of the virtual network mapping (VNM) fragment embedded in the request are rejected, and the problem of physical resource usage is weakened, a VNM algorithm based on the optimal subnet edge matching algorithm is proposed. After the VNM request is coarsened to the subnet, the breadth-first search algorithm is used to create the physical subnet candidate set, and the constraints of the virtual node and the coarsening network topology are complied with. The simulation results show that the proposed algorithm reduces the number of link mapping hops and can improve the acceptance rate and cost-benefit ratio of virtual networks. First of all, this paper analyzes the research background of manufacturing cost calculation and the research situation at home and abroad, discusses the advantages and disadvantages of standard cost calculation and studies and analyzes the principles, advantages and disadvantages of standard cost calculation in daily business activities. Second, design a new mathematical accounting model based on the mathematical model of standard cost calculation in daily business activities. This combines the advantages of standard costing and time-based activity costing, and provides theoretical support for manufacturing companies to use this accounting method. Finally, the research results of this paper are summarized, and the shortcomings of this paper are analyzed. Cost accounting method needs to be further studied.

The voice sensor is the core part of voice monitoring devices, and it is commonly drifted in long-term running. For this reason, the voice calibration of monitoring devices is essential. Several calibration methods had been introduced by leveraging expensive referred instruments or manual calibration methods. However, these methods are not only dependent on high-cost instruments, but also is impractical on isolated occasions. To overcome these issues, the feature fusion-based neighbor (FbN) model is proposed to calibrate voice sensors, via real-time low-cost ambient sensors. The FbN consists of a real-time awareness stage, feature selection stage, feature fusion stage, and prediction stage. First, voice data and exogenous low-cost sensor (LCS) data are simultaneously collected. Second, those low-cost sensor data are treated as individual features. The irrelevant features are empirically filtered out. The adopted exogenous features are temperature, humidity and air pressure. Third, the selected features are fused to obtain more representative features. Finally, distances between sensor data and represented features are calculated and sorted. The top-$k$ average distances are regarded as the predictive results. Experimental comparisons with several novelty methods show the effectiveness of the proposed FbN.

In this paper, the fuzzy neural network model is studied, the real-time regulation model of physical training intensity is analyzed and a real-time regulation system based on a fuzzy neural network is designed. The real-time, accurate and effective regulation of the physiological load intensity in the body of the exerciser is consistent with the predetermined goals of the training program. In this paper, we propose an RBF neural network, combined with the plan and demand of physical training operation situation sensing, and considering that most of the biological training operation data is fuzzy, this paper connects a fuzzy logic inference system and a neural network and proposes a network operation situation sensing model based on an RBF neural network structure. The RBF neural network and the traditional fuzzy neural network are compared. The experiments prove that this paper’s fuzzy neural network model has a faster training speed. In this paper, we use time-realistic control equipment to monitor the physical training process of athletes so that we can grasp the training situation of athletes in real-time and ensure that athletes can achieve better training results by changing training methods and changing training loads in time for those athletes who cannot reach their sports goals. In the process of physical fitness training monitoring, an effective monitoring of training, time-accurate regulation monitoring has the advantage of timely feedback on the training situation. This model has a better convergence effect during exercise and a higher accuracy of posture prediction during testing.

Frequency-modulated continuous-wave (FMCW) signals-based radar systems can outrun the optical and ultrasound sensors in dark and severe weather conditions. FMCW radar systems require a fast settling frequency synthesizer to reduce the chirp signal’s inactive and modulation times. This work proposes a new C-B and FMCW Transmitter based on Fast Settling Fractional-N DPLL (FS-FNDPLL) and ring-based pulse injection locking oscillator (R-PILO). The proposed FS-FNDPLL generates an ultra-fast low-noise smooth narrowband chirp by introducing an automatic controller-based TDC switching (AC-TDCSw) scheme in the forward loop of FNDPLL. Also, the proposed FS-FNDPLL employs a new background gain calibrated digital-to-time converter (BGC-DTC) as a fractional divider in the feedback path for the quantization noise cancellation (QNC). The proposed FMCW transmitter uses an R-PILO to produce fast switching adjacent carriers after generating a narrowband chirp using FS-FNDPLL. The main features of the proposed FMCW to accelerate settling time with AC-TDCSw, BGC-DTC and the integration of spur suppressing pulse generator (SSPG) in R-PILO enable ultra-fast chirps with less phase noise and spur levels. The proposed transmitter up-converts the 500MHz narrowband chirp signal onto four adjacent carriers for obtaining a 2GHz chirp at the C-band. The simulation results prove that the proposed FMCW Transmitter consumes 79mW power. Furthermore, the phase noise of the proposed FS-FNDPLL is reduced to $-113$dBc/Hz at 1MHz. The proposed FS-FNDPLL reduces the settling time to 1$\mu$s with the introduced AC-TDCSw scheme.

Real-time and fast recognition of all kinds of traffic participants in intelligent driving has always been a major difficulty in the research of internet of vehicles. With the advent of edge computing, we try to deploy an image recognition algorithm directly to the intelligent vehicles. However, the original image recognition algorithm is difficult to be directly deployed on the vehicles due to limited edge device resources. Based on this, a fast recognition model of vulnerable traffic participants based on depthwise separable convolutional neural network (DSCYOLO) is proposed in this paper. The algorithm can significantly reduce the convolutional parameter quantity and computing load, making it suitable for deployment on the vehicle-mounted edge embedded devices. In order to validate the effectiveness of the proposed method, its simulation results are compared with the main target detection models Faster R-CNN, SSD and YOLOv3. The results show that the recognition time of the proposed model is reduced by 80.28%, 66.80% and 86.74%, respectively, on the basis of a relatively high recognition precision. The model can realize real-time detection and fast recognition of vulnerable traffic participants, so as to avoid a large number of traffic accidents. It has significant social and economic benefits.

In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ($P_c$), computation time ($C_t$) and area ($A$) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ($P_c$), computation time ($C_t$) and area ($A$). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone$Ⓡ$ V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.

In this paper, a computer vision-based cashew nut grading system has been designed and implemented for classifying different grades of cashew nuts using combined features and machine learning approaches. The important task in the cashew nut grading system is to classify the whole and split down cashew nuts. Since these cashew nuts look very similar from the top view, it is a challenging task to classify the whole cashew nut and split down cashew nuts. Hence, a single-view image of cashew nut has been captured by placing a camera with a distance of 17cm (from the right side of the conveyor belt). The captured red, blue and green images are normalized and converted into hue, saturation and value color space. S channel from HSV image is used for segmentation process using Otsu threshold technique. The total numbers of features extracted are 275 and the features are texture (180), color (90), and shape (5). The constrained optimization-based feature selection method is used and 30 features are selected for further process. The Support Vector Machine (SVM) classifier is used for the classification, and the results obtained from different kernel functions are computed and compared. The 8-layer convolutional neural network (CNN) has been developed in this work for classification and to analyze the performance and accuracy. The accuracy of different machine learning classifiers like SVM 1-1, SVM 1-All and CNN model is also evaluated and compared. The overall accuracy obtained by SVM 1-All with kernel function radial basis for classification is 98.93%.

The current state-of-the-art single-person pose estimation methods require heavily parameterized models for accurate predictions. A promising technique to achieve accurate yet lightweight pose estimation is knowledge distillation. However, existing pose knowledge distillation methods rely on the most common large basic building blocks and a complex multi-branch architecture. In this study, we propose a Single-branch Lightweight Knowledge Distillation method to increase pose distillation efficiency for 2D Single-person pose estimation, termed SLKD2S. First, we design a novel single-branch pose knowledge distillation framework, which is composed of connected lightweight pose estimation stages. Second, we utilize a special pose distillation loss based on the joint confidence map. Finally, we only keep the initial stage and the first refinement stage to achieve a good performance. Extensive experiments on two standard benchmark datasets show the superiority of the proposed SLKD2S in terms of cost and accuracy, and the average detection accuracies are increased by 1.43% and 2.74% compared with the top-performing pose distillation method, respectively.

In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.

In this paper, a novel current mode (CM) building block termed Voltage differencing current conveyor transconductance amplifier (VDCCTA) is developed by combining the voltage differencing current conveyor (VDCC) and an operational transconductance amplifier (OTA). This modern active block VDCCTA is extended for applications such as a lossless inductor, filter design, and chaotic circuit design. An active inductor simulator (AIS) without any component matching is designed using the proposed VDCCTA block and a grounded capacitor as a first application that offers flexibility to model grounded positive active inductor (GPAI), grounded negative active inductor (GNAI), and floating positive active inductor (FPAI) circuits. Moreover, the proposed positive active inductor (PAI) can also be translated for multiple input single output (MISO) voltage mode (VM) universal filter with two external passive elements and chaotic circuitry. The characteristics of VDCCTA are verified with the CM multifunction filter, VM band-pass filter, and VM-MISO filter. A complete exercise of this newly reported VDCCTA block is analyzed for their port characteristics validation and the performance parameters using PSPICE simulation. Finally, experimental verification of the proposed AIS is tested to justify the theoretical and simulated results.

The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.

In recent research works on coverless text information hiding, there are two main problems to be solved: low hiding success rate and small hiding capacity caused by the small amount of redundant information in the cover text. In order to overcome these problems, a method of coverless information hiding based on the combination of Chinese character components is proposed. This method is based on the traditional “location tag $+$ keywords” mode for coverless information hiding, but with an improved design to extend the scope of available keywords for data hiding beyond the original cover texts. In our proposed method, each Chinese character in the keyword is split into two components: radicals and independent Chinese character, which are collected and will be recombined in pairs to generate the new Chinese characters. This method increases the hiding success rate and hiding capacity by generating Chinese characters that do not exist in the original cover text. The experimental result shows that the proposed method can utilize less size of carrier text database for efficient information hiding. When the size of carrier text database is reduced to 198MB, the highest hidden capacity and hidden success that can be achieved are 13.45 and 0.99, respectively.

Random number generator design is one of the practical applications of nonlinear systems. This study used random number generation and sound encryption application with a fractional chaotic system. Random numbers were generated with the Langford chaotic system, and a sound encryption application was carried out for the secure transmission of voice messages. Randomization performance of numbers was evaluated by employing NIST-800-22 statistical tests, which meet the highest international requirements. It was observed that the distributions of these generated random numbers reached the desired level of randomness after the examination. Unlike the integer-order random number generators widely used in the literature, the fractional-order Langford chaotic system was employed to generate and analyze random numbers and demonstrate their utilization in sound encryption. Random numbers generated from a fractional degree-based chaotic system developed in this study can be used in cryptology, secret writing, stamping, statistical sampling, computer simulations, dynamic information compression and coding.