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This paper presents an investigation of the design optimization in microstrip lines to reduce the crosstalk level using Fuzzy Logic. In microstrip lines length and spacing, termination conditions of interconnection and output impedance of gates are the major components that cause crosstalk. In order to design high speed printed circuit board (PCB) with optimum interconnection configuration, it is essential to reduce the crosstalk to its minimum tolerance level. A design methodology is proposed to correlate electrical parameters and physical configuration of lines to the crosstalk phenomena. This design is subsequently optimized using Fuzzy Logic to reduce the level of crosstalk. A set of experiments is carried out to demonstrate the capabilities of the design and optimization methods. The effect of the geometrical configuration of the lines on crosstalk, particularly the spacing, is highlighted.

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard.

In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.

Aggressive miniaturization has led to severe performance and signal integrity issues in copper-based interconnects in the nanometric regime. As a consequence, development of a proper analytical model for such interconnects is extremely important. In this work, an ABCD parameter matrix-based model is presented for fast and accurate estimation of crosstalk delay and noise for identically coupled copper-based nanointerconnect systems. Using the proposed model, the crosstalk delay and noise are estimated in copper based nanointerconnects for intermediate and global interconnects at the future integrated circuit technology nodes of 21 and 15 nm, respectively. Proposed model has been compared with SPICE and it is found that this model is almost 100% accurate as SPICE with respect to both the crosstalk delay as well as noise. Moreover, this model is as much as ~ 63 and ~ 155 times faster, respectively. From the crosstalk delay and noise analysis of unrepeated interconnects, it is observed that both delay and noise contribution will increase in scaled technology nodes. The same trend is observed also for the repeated interconnects. Also more number of repeaters and higher repeater sizes will be needed for delay minimization as we scale deeper. So as far as crosstalk induced effects are concerned, the copper interconnects will face a huge challenge to overcome in nanometer technology nodes.

In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented for the analysis of crosstalk induced delay. Several researchers have proposed analytical models for interconnects based on single-walled CNT (SWCNT), multi-walled CNT (MWCNT) bundle and most interestingly, spatially arranged mixed CNTs. Although, bundled SWCNTs and MWCNTs are easily realizable, but, practically it is almost impossible to fabricate a MCB with precise arrangements of SWCNTs and MWCNTs. Motivated by these facts, this paper presents a corner placement algorithm for randomly distributed SWCNTs and MWCNTs of different diameters in a MCB. The performance of MCB is compared with that of conventional bundled SWCNT and bundled MWCNT at different coupled interconnect lengths and spacing. Encouragingly, for a fixed cross-sectional area, the overall crosstalk induced delay of MCB reduces by 65.03% and 23.54% in comparison to the bundles having either SWCNTs or MWCNTs with smaller diameters, respectively. However, in contradiction to most of the previously reported results, bundled MWCNTs with larger diameters outperform the randomly distributed MCBs in terms of crosstalk performance.

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and overshoot/undershoot analyses for the application of signal interconnects. The results are compared with that of the traditional Cu-based interconnects. The results show that GNR is better than Cu as far as IR drop, SSN, gate oxide reliability and hot carrier reliability are concerned. Our investigation reveals that GNR can be better than the Cu interconnects from all aspects with a multilayer GNR structure. The present graphene-based interconnect technology needs to be advanced, so that the metal–graphene contact resistance is minimized and multilayer GNR structure with large number of graphene layers is supported.

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11nm and 8nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1mm long intermediate interconnects and less than 7% of that of copper interconnects for 5mm long global interconnects at 8nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

Compared with the traditional copper material, carbon nanotube (CNT) has been identified as one of the most potential materials for interconnects in nanometer regime due to higher performance. However, for CNT interconnects, most of the researches focus on voltage-mode signaling (VMS) scheme, whereas current-mode signaling scheme (CMS) is meagerly investigated. The paper proposes an equivalent circuit model of two-line coupled single-walled CNT bundle interconnects, which is applicable to both CMS and VMS schemes. In addition, the model takes capacitive and inductive crosstalk into consideration. In CMS and VMS interconnects, the performance of victim line in the time domain is studied according to decoupling technique and ABCD parameter matrix approach at local, intermediate and global levels, respectively. The influence of aggressor line on victim line is discussed because of dynamic crosstalk and functional crosstalk. Furthermore, the paper comparatively analyzes the performance advantage between CMS interconnects and VMS interconnects. The results show that CMS interconnects have lower output voltage swing and propagation delay than VMS interconnects in the same condition. In terms of noise, CMS scheme has higher advantage for lesser noise peak, noise width and noise area. Moreover, it is found that the results obtained by ABCD parameter matrix approach have great consistency with Advanced Design System simulation results.

In this work, we have presented the temperature-dependent analytical time domain model for top-contact multilayer graphene nanoribbon (TC-MLGNR) and side-contact multilayer graphene nanoribbon (SC-MLGNR) interconnects for 16nm technology node. Using this analytical model, the effective mean free path (MFP) is calculated for different temperatures and then the resistance of GNR interconnect is calculated. The lower resistance of MLGNR is one of the important factors to reduce interconnect delay. The equivalent capacitance for TC-MLGNR is also calculated. It is observed that the performance of graphene interconnects seriously deteriorates due to the presence of the interlayer capacitance. The presence of this interlayer capacitance increases the equivalent capacitance which is the dominant factor that inhibits the performance of TC-MLGNR interconnects. Further, the delay ratio between copper and TC-MLGNR for different interconnect lengths and for three different temperatures (233K, 300K, 378K) is calculated. It is observed that for longer interconnect lengths, the improvement in delay in TC-MLGNR is less as compared to traditional copper-based interconnect at low temperature. Further, power delay product (PDP) of copper and TC-MLGNR for different interconnect lengths and for three different temperatures is also calculated. It is shown that TC-MLGNR interconnects have better PDP than copper interconnects. The crosstalk analysis is performed to estimate the noise and overshoot/undershoot in TC-MLGNR and SC-MLGNR interconnects. It is shown that SC-MLGNR interconnect has better performance as far as the crosstalk is concerned as compared to that of Cu and TC-MLGNR interconnects.

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100$\mu$m and 1,000$\mu$m interconnect lengths, respectively.

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

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The visibilities measured by radio astronomical interferometers include non-astronomical correlated signals that arise from the local environment of the array. These correlated signals are especially important in compact arrays such as those under development for 21cm intensity mapping. The amplitudes of the contaminated visibilities can exceed the expected 21cm signal and represent a significant systematic effect. We study the receiver noise radiated by antennas in compact arrays and develop a model for how it couples to other antennas. We apply the model to the Tianlai Dish Pathfinder Array (TDPA), a compact array of 16, 6-m dish antennas. The coupling model includes electromagnetic simulations, measurements with a network analyzer, and measurements of the noise of the receivers. We compare the model to drift-scan observations with the array and set requirements on the level of antenna cross-coupling for 21cm intensity mapping instruments. We find that for the TDPA, cross-coupling would have to be reduced by three orders of magnitude in order to contribute negligibly to the visibilities.

An arrayed waveguide grating (AWG) router is optimised for use in an AWG-based optical add-drop multiplexer (OADM) of a WDM transparent optical network with 10 Gbit/s per channel and channel spacing of 25 GHz. Two different techniques to flatten the AWG frequency response are investigated. It is shown, by simulation, that the optimised AWG router of an OADM with fold-back configuration should have bandwidth similar to the channel spacing, good isolation to adjacent channels and low or moderate additional losses. Numerical results reveal that AWG routers with frequency response between the flat and conventional AWG responses are the best candidates.