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Half-T RC ladder networks (LNs) are proven to be first-order models of transmission lines (TLs) and interconnections. In this paper, the determination of LNs electrical characteristics, in terms of internal electrical parameters and number of cells, has allowed to calculate, in an approximated but very accurate way, the time delay and cutoff frequency of open-ended RC LN. Numerical examples on real designs confirm the validity of the proposed method in terms of robustness and accuracy.

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard.

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11nm and 8nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1mm long intermediate interconnects and less than 7% of that of copper interconnects for 5mm long global interconnects at 8nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16nm ITRS technology node. A $10\times 10$ standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10$\mu$m interconnect length at temperatures (233K, 300K and 378K). Our analysis shows that MLGNR exhibits ($\sim 1.5$–$2\times$) less SSN and ($\sim 1.5$–$3\times$) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233K), 53–32% (at 300K) and 52–30% (at 378K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233K), 57–29% (at 300K) and 57–26% (at 378K) less than that of Cu-based power interconnects.

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100$\mu$m and 1,000$\mu$m interconnect lengths, respectively.

This paper presents an analytical model of the origin of nonlinear crosstalk induced by the XPM-SMZI (Cross-Phase Modulation-Symmetric Mach–Zehnder Interferometric) phenomenon occurring in the TWSOA (Traveling Wave Semiconductor Optical Amplifier). We analyze the variation of nonlinear crosstalk with increasing logic levels and length of the input bit sequence. The investigation shows that alteration in high and low logic of bit sequence engenders changes in cross-phase modulation occurring in TWSOA and hence brings nonlinear crosstalk into the picture. The performance is evaluated on 4×4 switching interconnect with a TWSOA cavity length of 500$\mu$m, a width of 3$\mu$m, and a height of 0.8nm with 0.15A injection current in SMZI configuration operating at 10Gbps. The performance of the switch is also tested by comparing various combinations of bit logic inputs. The degradation is observed in the quality of service with an increase in the number of ‘1’s in bit sequence. The Extinction Ratio (ER) also deteriorates when a logic ‘1’s appears at consecutive places. This impairment in ER can be controlled by bias conditions of TWSOA. The promising crosstalk of $-30$dB has been achieved and is further validated by comparing with previously reported techniques.

Scanning Tunneling Microscopy and Spectroscopy have been used in an attempt to elucidate the electronic structure of nanotube systems containing two constituent shells. Evidence for modified electronic structure due to the inter-layer interaction in double-walled carbon nanotubes is provided by the experimental tunneling spectra and the contribution of the inner tube to the local density of states of the "composite" double-walled system is identified in agreement with previous theoretical calculations. An explicit correlation between the chirality of the two constituent tubes, the inter-wall interaction and the overall electronic structure for double-walled carbon nanotubes, is demonstrated by our experiments, showing that the effect the inner tube has on the overall electronic structure of double-walled nanotubes cannot be neglected, and is key to the opto-electronic properties of the system. We postulate that previous analysis of the opto-electronic properties on multiple-walled carbon nanotubes based purely on the outer layer chirality of the tube needs significant modification based on new understanding brought forth with our analysis.

The effect of La${}_{0.7}$Sr${}_{0.3}$MnO${}_{3-\delta }$ (LSM) coating on SS446 steel on air oxidation at 800${}^{\circ }$C was investigated by transmission electron microscopy. Dense and crack free thin LSM films were prepared by electrostatic spray deposition. The microstructural characterization was carried out on coated and uncoated interconnectors. A thin chromia scale at the alloy interface along with two spinel phases were observed after long term oxidation in both cases. Specimens exhibit, in addition, an SiO₂ layer at the interface with steel due to the high content of Si in the steel. Significant changes in the thickness, morphology and composition occurred in the reaction layer for the LSM coated steel. These effects are explained on the basis of changes in the diffusive fluxes during exposure to the oxidation treatment. The implications of these effects for the degradation mechanism of LSM-based interconnects are discussed.

Semiconducting, metallic and insulating nanowires are attractive building blocks in nanotechnology due to their small size and anisotropy. Moreover, it is possible to fabricate homogeneous or heterogeneous nanowires with high purity and crystallinity in a parallel and cost effective manner. Strategies have also emerged to position nanowires precisely on substrates to allow integration of nanoelectronic devices. In this chapter, we describe the fabrication and assembly of nanowires to form functional devices. Several fabrication strategies including vapor-liquid-solid (VLS) and electrodeposition in nanoporous templates are discussed. We detail advances made in the bottom-up integration of nanowires using patterned growth and directed assembly. Finally, some functional devices fabricated using nanowires are reviewed, and strategies to reduce errors and improve defect tolerance are discussed.