Narrow Results

The electrical characteristics of the ferroelectric field-effect transistors (FeFETs) are analyzed numerically and presented in this paper. The metal–ferroelectric–insulator–semiconductor field-effect transistor (MFISFET), among the primary structures, is taken into consideration. The nonsaturated hysteresis loop of the ferroelectric material is described by a novel analytical calculation for the relation of polarization against electric field (P–E). The combined impact of the nonuniform concentrations of electric field charge throughout the channel and the nonsaturated polarization of ferroelectric layers are considered to create a more realistic modeling. The proposed research work also provides an in-depth study of the electrical properties of the GAA-based Nanowire FeFET, exploring important variables including transconductance, subthreshold swing, as well as a threshold voltage. The analytical insights derived from the mathematical framework are consistent with the simulated results obtained with the ATLAS 3D simulator.

The progress of silicon technologies we have witnessed in the last twenty years has traced the path to the unprecedented revolution of information technologies, which has changed almost everybody's lifestyles. Apparently, this has happened with a little big help from TCAD tools. Big, because few major advancements have been achieved through the clever exploitation of non-conventional simulation tools, and because everyday device optimization deeply relies on TCAD tools. Little, because the qualitative feeling is that the technology would have progressed anyway, through the work of many highly-skilled technology experts, even without simulation guidelines. The purpose of this paper is to review the state-of-the-art of the field of the transport modeling of electron devices, trying to grasp the essence of the most relevant simulation models proposed so far, whence to contribute to spur the activity on the fundamental modeling of carrier transport.

A new method for investigating quantum confinement effects in MOSFETs is presented. The method is based on the numerical solution of the Schrödinger and Boltzmann system of equations. A quantum Boltzmann equation is developed by replacing the classical potential with a quantum potential. The technique naturally accounts for highly nonequilibrium effects including velocity overshoot. The subbands are calculated and then populated using nonequilibrium statistics. Modeling results show the electron concentration and electron current density peaks shifted away from the interface. Calculations show reduced channel concentration which leads to lower drain current for the quantum case. A quantum distribution function is obtained.

The paper presents a simulation study of the physics and performance of novel asymmetric tunneling solutions for the sub-100nm MOSFET technology. Two device structures have been investigated: Schottky Tunneling Source MOSFET and band-to-band P⁺-N⁺ Tunneling Source MOSFET. The Schottky MOSFET exhibits degraded Ion and subthreshold swing (in spite of improved DIBL). On the other hand, the novel PNPN MOSFET shows high Ion/Ioff and steep subthreshold behavior.

Ultra-thin body Double Gate MOS structures with strained silicon are investigated by solving the 1-D Schrödinger and Poisson equations, with open boundaries conditions on the wave functions in the gate electrodes. The electrostatics of this device architecture and its dependence on the amount of strain and on the thickness of the silicon layer is analyzed in terms of subband structure, subband population, carrier distribution within the strained-silicon layer, charge-voltage characteristics and gate tunneling current.

Silicon carbide (SiC) unipolar devices have much higher breakdown voltages than silicon (Si) unipolar devices because of the ten times greater electric field strength of SiC compared with Si. 4H-SiC unipolar devices have higher switching speeds due to the higher bulk mobility of 4H-SiC compared to other polytypes. In this paper, four commercially available SiC Schottky diodes with different voltage and current ratings, VJFET, and MOSFET samples have been tested to characterize their performance at different temperatures ranging from -50°C to 175°C. Their forward characteristics and switching characteristics in this temperature range are presented. The characteristics of the SiC Schottky diodes are compared with those of a Si pn diode with comparable ratings.

In this paper, we have fabricated and compared the performance of lateral enhancement-mode GaN MOSFETs with linear and circular geometries. Circular MOSFETs show 2 to 4 orders of magnitude lower leakage current than that of linear MOSFETs. We also studied short channel behaviors and found that they are similar to those previously reported Si MOSFET.

We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal directions was investigated for different channel geometries. The biasing condition which enables the simultaneous activation of all channels and gives rise to volume inversion is discussed.

The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be exploited for bio-applications. In this manuscript TCAD results are presented on the analog and digital performance of the Screen-Grid Field Effect Transistor. The results are compared to the operation of an SOI-MOSFET and a finFET.

We have fabricated, characterized and compared the performance of lateral enhancement-mode GaN MOSFETs on as-grown and RIE-etched surfaces with 900 and 1000°C gate oxide annealing temperatures. Both subthreshold swing and field effect mobility show 1000°C is the optimal annealing temperature for the PECVD gate oxide in our MOSFET process.

We have fabricated, characterized and compared the performance of lateral n-channel 4H-SiC MOSFETs on (000-1) oriented substrates, using two different gate oxide processes. These processes include low-temperature deposited oxide and plasma-enhanced CVD oxide. Different MOSFET parameters, such as field-effect mobility, threshold voltage, Hall mobility and inversion sheet carrier concentration has been compared for the two processes.

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior.

Hall electron mobility in buried QW InGaAs channels, grown on InP substrates with HfO₂ gate oxide, is analyzed experimentally and theoretically as a function of top barrier thickness and composition, carrier density, and temperature. Temperature slope α in μ ~T^α dependence is changing from α=-1.1 to +1 with the reduction of the top barrier thickness indicating the dominant role of remote Coulomb scattering (RCS) in interface-related contribution to mobility degradation. Insertion of low-k SiO_x interface layer formed by oxidation of thin in-situ MBE grown amorphous Si passivation layer has been found to improve the channel mobility, but at the expense of increased EOT. This mobility improvement is also consistent with dominant role of RCS. We were able to a obtain a reasonable match between experiment and simple theory of the RCS assuming the density of charges at the high-k/barrier interface to be in the range of (2-4)×10¹³ cm^-2.

Insulated gate n-channel enhancement mode InGaAs field effect transistors with the GdScO₃ high-k dielectric have been fabricated and studied. The low frequency noise was high indicating a high interface density of traps. Trap density and its dependence on the gate voltage have been extracted from the noise and conductance measurements.

We have fabricated and investigated several types of GaN MOSFETs with normally-off operation. The recessed-gate GaN MOSFET is preferred for normally-off operation, because the threshold voltage (V_th) of the device can be easily controlled, but it suffers from relatively modest current drivability which must be improved by adopting appropriate device structure and/or process. Enhanced performances have been achieved in this work by combining the recessed-gate technology with additional processes, such as: the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, the post-deposition annealing of gate oxide to decrease the gate leakage current, the re-growth of n+ GaN layer for source/drain to improve the access resistance and V_th uniformity, the stress control technology to achieve extremely high 2-D electron-gas density (2DEG) on source/drain and decrease the series resistance, and the use of the p-GaN back-barrier to decrease the buffer leakage current. The GaN-based FinFET with very narrow fin was also investigated as a possible candidate for high performance normally-off GaN MOSFETs.

Power semiconductor devices are important for numerous applications with power conversion being an important one. Wide energy gap semiconductors SiC and GaN have properties that make them attractive for such applications. Among these properties are high thermal conductivity, high breakdown electric field, wide energy gap, low intrinsic carrier concentration, high thermal stability, high saturation velocity and chemical inertness. These lead to low on-resistance, high breakdown voltage, high frequencies, small volume, and small passive inductors and capacitors. These desirable properties are offset by the higher material costs and higher defect densities. Although wide energy gap devices have been in development for many years, only recently have they become available commercially. Their main competition is silicon power devices with breakdown voltages up to 8000 V and very high surge current capacity. However, silicon power devices are approaching their material limits and wide energy gap devices are beginning to have an impact in the power electronics space. SiC has the advantage of substrates with diameters approaching 150 mm and the ability to grow thermal SiO₂. GaN has the heterojunction advantage, but no viable substrate technology. In fact, a large portion of SiC production is used for GaN substrates. GaN material development has also benefited significantly from the development of optical devices, e.g., light-emitting diodes and lasers.

Alternative channel materials with superior transport properties over conventional silicon based systems are required for supply voltage scaling in CMOS circuits. Group III-Sb's are a candidate for high mobility p-channel applications due to a low hole effective mass, large injection velocity in scaled devices and the ability to achieve enhanced hole mobility in strained quantum wells (QW). Multiple challenges in antimonide MOSFET development are assessed and developed technologies were implemented into p-channel MOSFET fabrication with a low thermal processing budget of 350°C. These challenges include growth of “bulk” GaSb and bi-axial compressively strained In_xGa_1-xSb QW channels on lattice mismatched GaAs substrates, reduction of interface trap state density (D_it) at the III-Sb/high-k oxide interface and avoiding ion implanted source and drain contacts with high temperature activation annealing. A “self-aligned” single mask p-channel MOSFET fabrication process was developed on buried In_0.36Ga_0.64Sb QW channels using intermetallic source and drain contacts. The first “gate-last” MOSFET process on In_0.36Ga_0.64Sb QW channels with pre-grown epitaxial p⁺⁺-GaSb contacts is demonstrated. InAs has been proven to be an excellent etch stop layer when using an optimized tetramethylammonium hydroxide (TMAH) etch of p⁺⁺-GaSb to prevent InGaSb QW damage.

This work presents multivariate regression polynomial as a versatile and efficient method for DC modeling of modern transistors with very different underlying physics including MOSFET (metal-oxide-semiconductor field-effect transistor), MESFET (metal–semiconductor field-effect transistor), HBT (heterojunction bipolar transistor), HEMT (High-electron-mobility transistor) and a novel silicon-on-insulator four-gate transistors (G⁴FET). A set of available data from analytic solution, TCAD simulation, and experimental measurements for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. The developed model expresses the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of training data set. The continuity of the resulting polynomial and its first and second order derivatives make it particularly suitable for implementation in a circuit simulator. The model also provides a method for further simplification based on prior knowledge of the underlying physical mechanism and shows excellent predictive capability for different kinds of devices. This can be very useful for modeling deep-submicron emerging devices for which any closed-form analytical solution is not yet available.

Ga₂O₃ has gained worldwide interests for next-generation power electronics because its large critical field strength stemming from an ultra-wide bandgap promises miniaturized circuits and systems with high conversion efficiency. Intense pursuit of Ga₂O₃ power devices stimulated by early demonstrations of high-voltage Ga₂O₃ field effect transistors (FETs) has brought about tremendous advancements in this new technology, whose strong radiation tolerance and high thermal stability also befit harsh-environment applications. In this paper, we review the various types of depletionand enhancement-mode Ga₂O₃ FETs — which have predominantly been lateral devices — for power switching and radiation-hard electronics. The development of vertical Ga₂O₃ transistors based on a low-cost, highly-manufacturable ion implantation doping process will also be discussed.

Silicon technology enabled most of the electronics we witness today, including power electronics. However, wide bandgap semiconductors are capable of addressing high-power electronics more efficiently compared to Silicon, where higher power density is a key driver. Among the wide bandgap semiconductors, silicon carbide (SiC) and gallium nitride (GaN) are in the forefront in power electronics. GaN is promising in its vertical device topology. From CAVETs to MOSFETs, GaN has addressed voltage requirements over a wide range. Our current research in GaN offers a promising view of GaN that forms the theme of this article. CAVETs and OGFETs (a type of MOSFET) in GaN are picked to sketch the key achievements made in GaN vertical device over the last decade.