Journal of Circuits, Systems and Computers

A new high input impedance filter employing three current feedback amplifiers (CFAs) and six passive elements, three of them are grounded, is presented. The proposed circuit offers the following advantages: simultaneous realization of lowpass (LP), bandpass (BP) and highpass (HP) filtering functions, employs two grounded capacitors, exhibits high input and low output impedances which permits easy cascade connection, low passive sensitivity figures and orthogonal control of resonance frequency (ω_o) and bandwidth (ω_o/Q). PSPICE simulation results are given to verify the theoretical calculations.

Several ZVS/ZCS (zero voltage switching/zero current switching) snubbers have been proposed in the past to minimize the losses and EMI in boost PFC. In these topologies, the commutation energies are reflected to the load or source to achieve energy conservation. However, this energy can also be utilized in a way to further improve the performance of the PFC and this paper is a first step in this direction. Here, we will propose a new topology to minimize the crossover distortion in boost rectifier. The main characteristic of the proposed topology besides ZCS/ZVS switching is that it also improves the crossover distortion. A prototype system was built and tested to verify the proposed topology.

In this paper, the discrete Fourier transform is used to determine the coefficients of a transfer function of a new generalized two-dimensional system of second-order: Ex(i₁ + 2, i₂ + 2) = A₀x(i₁ + 1, i₂ + 1) + A₁x(i₁ + 1, i₂) + A₂x(i₁, i₂ + 1). The algorithm is straightforward and has been implemented using the software package Matlab™. A step-by-step example illustrating the application of the algorithm is presented.

Many of the new high-speed high-integration density Integrated Circuits (ICs) and future generation of microprocessor powering requirements can be successfully achieved with voltage-mode hysteretic control applied to interleaved multiphase Point-of-Load (POL) DC–DC converters or Voltage Regulator Modules (VRMs). This is because of the several advantages that can be achieved by combining the advantages of hysteretic control and interleaving. However, there are several challenges in combining the two techniques, the most prominent being the current sharing and equalization between the interleaved phases. In this communication, we present a solution based on a real-time DSP controller. Challenges of the implementation will be discussed and experimental results obtained from a prototype will be presented.

It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX decomposition problem and has been studied in Ref. 1. This paper improves on the results of Ref. 1 in two ways: (a) we propose a method to speed up the algorithms in Ref. 1, and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of Ref. 1.

This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

This paper presents novel CMOS realizations of the operational floating conveyor (OFC) based on novel block diagrams. It also introduces novel applications based on one of the proposed OFC realizations. The proposed OFC realization provides a wide bandwidth and a large gain bandwidth product. Hence, it exhibits wide bandwidth at higher gains. All the circuits in this paper are designed following a fair comparison criterion. The supply voltages are ±1.5 V. The reference DC current source I_B is taken as 50 μA. The CMOS model for all circuits is identical. The transistor model is 0.5 μm CMOS process provided by MOSIS (AGILENT).

This paper presents a new method for the design of variable fractional delay (VFD) FIR digital filters using Genetic Algorithm (GA). Each sub-filter of Farrow structure is designed individually with defined accuracy and bandwidth. A variable mutation probability is also employed, which improves the accuracy of the solution. Compared with existing methods, it reduces the computational complexity and enhances the design flexibility. Furthermore, a simple GA is used to compute the filter coefficients in canonic singed digit (CSD) representations. Since this algorithm selects the initial population in CSD representation and searches for the digits between [-1 1], most of the digits become zero. The filter multipliers can be built with simple shift registers and adders, resulting in a high-speed and low-power filter implementation. Multiplier-free structure typically shows 11.4% saving in power and 17.2% reduction in area consumption.

For packet video, information loss and bandwidth limitation are two factors that affect video playback quality. Traditional rate allocation approaches have focused on optimizing video quality under bandwidth constraint alone. However, in the best-effort Internet, packets carrying video data are susceptible to losses, which need to be reconstructed at the receiver side. In this paper, we propose loss aware rate allocations in both group-of-block (GOB) level and macroblock level, given that certain packets are lost during transmissions and reconstructed using simple interpolation methods at the receiver side. Experimental results show that our proposed algorithms can produce videos of higher quality when sent over lossy Internet.

Dynamic power management is a technique to reduce power consumption of electronic systems by selectively shutting down idle components. In this paper, an intelligent approach is presented based on reinforcement learning to predict the best policy amongst the existing DPM policies. Reinforcement learning is a computational approach to understanding and automating goal-directed learning and decision-making. The effectiveness of this approach is demonstrated by an event-driven simulator, which is designed using JAVA for power-manageable embedded devices. The results of the experiments conducted in this regard establish that the proposed DPM scheme enhances power savings by 10 to 28%.