Journal of Circuits, Systems and Computers

In this paper, we address the DRAM storage assignment problems of variables with an objective of maximizing the number of page/burst mode accesses. Specifically, (1) we solve the problem of variable alignment to memory for maximizing the use of page accesses by proposing a technique, called zone_alignment, which is based on the combination of an efficient 0-1 ILP (integer linear programming) formulation and the utilization of temporal locality of variables' accesses in code and (2) the approach used in (1) is then applied to solve the problem of variable alignment for maximizing the use of burst accesses. Surprisingly, the execution of the ILP formulation used in (2) is relatively much faster than that used in (1) and nevertheless, the (optimal) formulation in (2) produces much better results than that by the existing techniques whereas the (optimal) formulation in (1) produces almost the same or slightly improved results, indicating that the problem with page accesses and the problem with burst accesses must be treated completely separately. (3) Finally, by utilizing the techniques in (1) and (2), we propose solutions to two extended DRAM architectures: (a) DRAMs with the capability of both of page and burst access modes and (b) DRAMs with multiple banks. We provide a set of experimental data to show the effectiveness of the proposed techniques.

A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement.

DC offset and high flicker noise are the main problems for the direct conversion CMOS mixer design. A novel even harmonic switching mixer implemented in a standard 0.18 μm CMOS process for applications in 2.45 GHz direct conversion receivers is proposed. The mixer circuit overcomes the problems of DC offset and high flicker noise. It achieves -8.24 dB gain, 5.2 dB DSB noise figure at 100 KHz, 17.25 dBm IIP3 and zero DC power consumption.

Along with the fast development of dual-threshold voltage (dual-V_t) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-V_t technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

This work describes a novel technique for automating the post-fabrication circuit tuning process. A training set that characterizes the behavior of the circuit under test is first constructed. The data in this set consists of input measurement vectors with no output attributes, and is clustered via unsupervised learning algorithm in order to explore its underlying structure and correlations. The generated clusters are labeled and utilized in circuit tuning by calculating the value(s) of the tuning parameter(s). Three prominent and fundamentally different unsupervised learning algorithms, namely, the self-organizing map, the Gaussian mixture model, and the fuzzy C-means algorithm are employed and their performance is compared. The experimental results demonstrate that the proposed technique provides a robust and efficient circuit tuning approach.

A new algorithm that efficiently calculates fixed polarity Reed–Muller (FPRM) expansions for ternary functions is presented in this paper. The algorithm starts from the truth vector representation of a ternary function and recursively generates all elements of the input function's polarity matrix. Computational costs for this algorithm are derived and they are smaller than in other existing methods for generating the complete polarity matrix when n ≤ 3.

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM³) switch which is a three-stage Clos-network switch with buffered center stage. The CFM³ deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM³ is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM³ switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM³ achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.

We have developed a domino logic synthesis system with a new technology mapping algorithm based on a bin packing algorithm that reduces the levels of the circuits and considers the complexity of domino primitive cells. Domino logic circuits have 20–50% performance advantage over static circuits. By using this system, designing domino logic circuits becomes much easier than manual design. The primary reason is that logic design is completely automated by the system. The second reason is that domino primitive cell layout is simplified by our new technology mapping algorithms that considers the complexity of domino primitive cells.

Six novel first-order filters with voltage input, voltage and current outputs employing a single fully differential current conveyor are proposed, three of which are canonical. All the circuits employ a grounded capacitor; and realize all-pass, low-pass and/or high-pass functions. Some circuits provide five distinct first-order functions or six functions with additional output stages. The proposed circuits are verified through computer simulation results.

A novel radix-3/9 algorithm for type-III generalized discrete Hartley transform (GDHT) is proposed, which applies to length-3^p sequences. This algorithm is especially efficient in the case that multiplication is much more time-consuming than addition. A comparison analysis shows that the proposed algorithm outperforms a known algorithm when one multiplication is more time-consuming than five additions. When combined with any known radix-2 type-III GDHT algorithm, the new algorithm also applies to length-2^q3^p sequences.