Journal of Circuits, Systems and Computers

A novel high speed linear tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode is proposed. Using this OTA, we construct a high speed fuzzifier and implement trapezoidal/triangular functions with all parameters (slope, width, and position) independently and continuously tunable, and excellent for low voltage applications. Computer simulations verify the performance of this circuit, showing high speed (up to 100 MHz) and a high support range (up to 2.5 V).

A novel filtering topology with a single input and three outputs (SITO) employing a single four-terminal current feedback amplifier (CFA) with an external compensation pin, such as AD844, two operational amplifiers (OAs), and as many resistors is presented. The circuit offers the features of simultaneous realization of lowpass (LP), bandpass (BP), and highpass (HP) filtering functions, free from component matching conditions, cascadability due to high input and low output impedances, orthogonal/independent adjustment of the filtering parameters, and low active and passive sensitivities. PSPICE simulation results are included to confirm the theoretical results.

This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.

A high-frequency highly linear tunable CMOS multiple-output operational transconductance amplifier (MO-OTA) for fully balanced current-mode OTA and capacitor (OTA-C) filters is presented. The MO-OTA is based on the cross-coupled pairs at the input and provides two pairs of differential outputs. A simple common-mode feedback (CMFB) circuit to stabilize the DC output levels of the MO-OTA is also proposed and two such CMFB circuits are used by the MO-OTA. The proposed MO-OTA is suitable for relatively low voltage (2.5 V) applications as its circuit has only two MOS transistors between the supply and ground rails. Simulated in a TSMC 0.25 μm CMOS process using PSpice, the MO-OTA has at least ± 0.3 V linear differential input signal swing with a single 2.5 V power supply and operates up to 1 GHz frequency. The MO-OTA has a THD less than -46 dB for a differential input voltage of 0.9 V_p-p at 10 MHz, dynamic range (DR) at THD = -46 dB is over 50 dB, and power consumption (with the common-mode feedback circuit) is below 8 mW for the whole tuning range. A fully balanced multiple loop feedback current-mode OTA-C filter example using the proposed MO-OTA is presented. This example also shows that the current-mode follow-the-leader-feedback (FLF) structure can achieve good performances for OTA-C filter design.

Implementing a quantum computer at the circuit level has emerged as an important field of research recently. An important topic of building a general-purpose quantum computer is to implement classical Boolean logic using quantum gates and devices. Since the Toffoli gate is universal in classical Boolean logic, any classical combinational circuit can be implemented by the straightforward replacement algorithm with auxiliary qubits as intermediate storage. However, this inefficient implementation causes a large number of auxiliary qubits to be used. In this paper, a systematic procedure is proposed to derive a minimum space quantum circuit for a given classical combinational logic. We first formulate the problem of transforming an m-to-n bit classical Boolean logic into a t-bit unitary quantum operation. The eligible solution set is then constructed such that a solution can be found simply by selecting any member from this set. Finally, we show that the algorithm is optimal in terms of the space consumption.

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults.

It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing.

In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

This paper describes the design and implementation of simple fuzzy logic controller (SFLC) for a nonlinear quasi-resonant converter (QRC). It is shown that the two-dimensional rule table of conventional FLCs (CFLCs) used in power converters can be reduced to one-dimensional rule table using SFLC. The proposed SFLC reduces the memory space and computing time of the fuzzy algorithm. The tuning of scaling factors and the generation of fuzzy rules are also easier when compared with CFLC. As a result, realizing SFLC in a Microcontroller or Digital Signal Processor (DSP) is made simple. The proposed controller structure is universal and it can be directly applied to any of the dc–dc converter topologies. In this paper, the application of SFLC is successfully verified for the voltage control of Extended Period (EP)-ZCS/ZVS-QRC through simulation and experimental studies using TMS320F2407A Processor. The ability of SFLC, compared to CFLC, to achieve good transient response for load variations and supply disturbances is demonstrated.

Mobile communication has a great potential to the users due to fulfilling the dreams of real-time multimedia communication like voice, image, and text. The huge amount of data redundancy in still image should be compressed using exact image compression algorithm (ICA) before transmitting via wireless channel. Thus, an ICA should be adaptive, simple, and cost-effective and suitable for feasible implementation. Hardware implementation of the different algorithms has improved using modern, fast, and cost-effective technologies. The main aim of this paper is to review and demonstrate various ICAs developed based on image transmission via wireless channel as well as their hardware implementation. Finally, this review makes bridge for researchers to the future relative studies between different algorithms and architectures, and stands as a reference point for developing more controlling and flexible structures.