Journal of Circuits, Systems and Computers

Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-stream-based processing with the decentralized parallel application-specific data-dominated processing, provide a drastically higher performance and lower power consumption than the traditional CPU-centric systems. They do it at much lower costs and shorter times to market than the not reconfigurable hardware solutions. They also provide the flexibility that is often required for engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, the reconfigurable computing (RC) systems are adequate for a very broad class of applications across different industry sectors. In this paper, the basic definitions, concepts and features of reconfigurable systems are discussed, as well as their role, purposes they serve and applications that can significantly benefit from them. Also, a comparison of the hardwired systems, RC systems and CPU-centric systems is made, and some main concepts of an effective and efficient reconfigurable computing are discussed. Subsequently, the classification of the RC systems is introduced and their various architecture classes are overviewed. This is followed by a discussion of some major drivers and requirements of the recent and future developments in the modern RC system area, and an overview of the recent and future development trends in the RC architectures. The reconfigurable system area is a very promising, but quite a new field. New opportunities have been opened for this field through introduction of the system-on-a-chip technology, and a big progress has been made in the recent years. Many different reconfigurable devices and computers became commercially available. Nevertheless, multiple aspects of the RC systems, their development and their supporting tools still belong to the open research or development topics.

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

This paper introduces a novel method for the conversion of synchronous cryptographic circuits into equivalent asynchronous ones. The new method is based on ASERT (Asynchronous Scheduling by Edge Reversal Timing), a fully decentralized timing signaling and synchronization algorithm. From a synthesizable HDL code, an asynchronous timing network, made from standard cells libraries, is generated in order to replace the clock tree of the target circuit. ASERT works with matched delays, local clocks or any equivalent way of determining, statically or dynamically, the operating time of each functional unit. Synchronous to asynchronous conversion of three different cryptographic circuits, including the fully synthesized netlists of AES, Reed-Solomon decoder, and RSA cipher cores, are presented.

Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.

Modular exponentiation is a basic operation in cryptosystems. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. The efficiency of the modular exponentiation, in turn, depends mainly on that of modular multiplications as the former is somehow a repetition of the latter. One of the methods that computes the modular power is the sliding-window method, which pre-processes the exponent into zero and nonzero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel System-on-Chip (SoC) implementation for computing modular exponentiation using the sliding-window method. We also propose a hardware-only implementation for that operation. The partitioning strategy used in both approaches allows constant-length nonzero partitions, which increases the average number of zero partitions and so decreases that of nonzero partitions. The partitioning strategy allows variable-length zero partitions. The hardware/software co-design implements the modular multiplication on hardware and the rest of the system in software. We provide a useful comparison of the SoC-based implementation against hardware-only implementation. Both of the proposed implementations can be used in any industrial embedded system that needs to secure the handled information.

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

This paper presents an overlapping block selection method to determine the dominant macroblock (MB) in multi-frame skipping transcoding to improve picture quality. A non-intra MB in a non-skipped frame should be predicted by a block in another non-skipped frame. The re-constructed motion vector (MV) between two non-skipped frames accumulates prediction error. As the number of frames between two non-skipped frames is increased, such prediction error, or called mismatch error, is also increased. To reduce the impact on the transcoding quality caused by the prediction error, we improve the traditional overlapping block selection method, and propose a most approximate overlapping block to help to determine a dominant MB. In the proposed method, the location of an overlapping block is calculated by adding the accumulated MVs and the position of the current MB. The accumulated MVs are not the real MVs for MBs but the approximate vectors for 16 × 16 overlapping blocks. Simulation shows that the proposed method has a higher performance than the traditional method.

A transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. It exploits MOS transistors in subthreshold region and dissipates 670 nA at DC. Despite this extremely low quiescent current value, the amplifier exhibits a DC gain of about 80 dB, and a gain-bandwidth product and phase margin around 2 MHz and 70°, with a load capacitance of 500 fF. Besides, working in class AB, the solution provides a slew rate equal to 27 V/μs. With exception of the DC gain, these performances represent an improvement with respect to comparable solutions, and are obtained while halving the area occupation.

There has been intensive research in memoryless nonlinear behavioral modeling of power amplifiers (PAs). But in broadband communication systems, memory effects of PAs can no longer be ignored and traditional memoryless model cannot accurately characterize the input-output relationship of PAs. In order to treat memory effects and reduce the complexity of general Volterra model, a new behavioral PA model based on modified Volterra series is proposed. Since the characteristics of power amplifiers change during transmission time, a recursive least squares algorithm with size-fixed observation matrices is developed to update the parameters of the PA model. This identification algorithm, which uses only the latest sample data to identify the parameters, can decrease computational complexity and data storage space needed for identification. Simulations are carried out to validate the performances of the proposed PA model and identification algorithm.

This work is aimed at generalizing the design of continuous-time second-order filters to the non-integer-order (fractional-order) domain. In particular, we consider here the case where a filter is constructed using two fractional-order capacitors both of the same order α. A fractional-order capacitor is one whose impedance is Z_c = 1/C(jω)^α, C is the capacitance and α (0 < α ≤ 1) is its order. We generalize the design equations for low-pass, high-pass, band-pass, all-pass and notch filters with stability constraints considered. Several practical active filter design examples are then illustrated supported with numerical and PSpice simulations. Further, we show for the first time experimental results using the fractional capacitive probe described in Ref. 1.

We propose a simpler and latency-reduced instruction scheduler, called chrono-scheduling algorithm, which avoids large and difficult instruction wake-up in order to reduce power consumption and latencies. The key idea of this scheduler is to extract and record all possible information about the future execution of an instruction during its issue, so as not to look for this information again and again during wait stages at the reservation stations. Therefore, an instruction can be issued with the information about at what cycle its operands must be captured and when it must be executed. The first implementation is targeted to processors that have constant latencies like many embedded microcontrollers, most vector processors without data cache, etc. Its main advantages are: no tags, no renaming, and much simpler waiting stations. When compared with classical dynamic schedulers, chrono-scheduling provides approximately the same CPI but with simpler overall circuitry and presumably higher clock speed (mainly because of its simplified stations).

This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.