Journal of Circuits, Systems and Computers

An integrated current mode high impedance input stage designed for Electrocardiography (ECG) systems (or low frequency general applications) is presented. This feature becomes necessary when a two-electrodes ECG apparatus is used (e.g., in fetal ECG or heart monitoring in extreme sports) and a good response of the system to common mode signals is required. The proposed input stage, based on a bootstrap topology that simultaneously increases the ECG electrodes input impedance (from 5 ÷ 50 kΩ to about 50 MΩ) and amplifies the applied signal, is implemented by using a configuration that employs only two second generation current conveyors for each electrode. Post-layout simulations have proved that the proposed system is quite not sensible to electrodes mismatch and battery discharge.

Continuous valued number system is a novel number system which can be employed for developing analog signal processing units. It is a continuous number system which is represented by a set of continuous digits. One of the main features of this system is that digits share information, and have a digit-level redundancy. This redundancy is used to protect the digits against environment imperfections when implemented by analog circuits. In this paper, integrity of this number system in representing real values is explored. The study is required to show the effect of implementation imperfections which is an indicative of its feasibility. Effects of possible errors and error threshold for implementing this system are studied in this paper. An error recovery method is proposed, which enhances this number system representation. An efficient error recovery method extends the application of this number system in high density memory and storage devices for hardware implementations of neural networks.

Aiming at such an application of wireless mesh sensor network (WMSN) so that continuous flow is transmitted, this paper proposes a model "maximum lifetime maximum throughput" based on the ant colony algorithm and minimum cost maximum flow method to address the routing issue between sensor nodes and multiple gateways in WMSN. In the proposed model, a sensor node is allowed to connect through more than one of the available gateways to the Internet. Between the source node and each gateway, a routing path with minimum link cost and maximum available bandwidth is attempted to be found. Then, considering the bandwidth demand of the flow originating from the sensor node and the available bandwidth on each optimal path, the flow traffic is allocated to appropriate gateways. Simulation results have shown that the proposed model not only prolongs network lifetime, but also improves network throughput.

The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.

Although using table to implement routing algorithm has some advantages in network-on-chip (NoC), the router queries the routing table whenever a packet is to be forwarded. The querying time significantly increases the packet delay even if some methods have been proposed to shorten the table size. In mesh-based NoC, statistics shows that two neighbor routers have the same routing options for over 50% packets, on average. In this paper, we propose a technique to let packets pass through some routers without querying the routing table. Consequently, the time to query the routing table is significantly decreased. Simulation results show that this leads up to 16% decrease of average packet delay.

Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent fan-out nodes (RFONs) within combinational subcircuits are a major source of topological correlation. We identify two more sources of topological correlation in clocked sequential circuit: sequential RFONs, which are nodes within a clock network where the clock paths to more than one flip-flop branch out; and sequential branch-points, which are nodes within a combinational block where combinational paths to more than one capturing flip-flop branch out. Dealing with all sources of correlation is unacceptably complicated, and we therefore show how to sample a handful of correlation sources without sacrificing significant accuracy in the yield. A further reduction in computation time can be obtained by sampling only those nodes that are likely to affect the yield. These techniques are applied to yield analysis using statistical static timing analysis based on discrete random variables and also to yield analysis based on Monte Carlo simulation; the accuracy and efficiency of both methods are assessed using example circuits. The sequential RFONs suggest that timing yield may be improved by optimizing the clock network, and we address this possibility.

This paper deals with the problem of globally delay-dependent robust stabilization for Takagi–Sugeno (T–S) fuzzy neural network with time delays and uncertain parameters. The time delays comprise discrete and distributed interval time-varying delays and the uncertain parameters are norm-bounded. Based on Lyapunov–Krasovskii functional approach and linear matrix inequality technique, delay-dependent sufficient conditions are derived for ensuring the exponential stability for the closed-loop fuzzy control system. An important feature of the result is that all the stability conditions are dependent on the upper and lower bounds of the delays, which is made possible by using the proposed techniques for achieving delay dependence. Another feature of the results lies in that involves fewer matrix variables. Two illustrative examples are exploited in order to illustrate the effectiveness of the proposed design methods.

The famous chaotic circuit known as Chua's oscillator, despite the robustness of the chaotic behavior to parametric mismatches, requires the construction of noncommercial valued inductor. A low cost inductorless version of Chua's oscillator is presented. The chaotic behavior of the circuit is verified by PSpice simulation and also by experimental study on a circuit breadboard. The results lead to excellent agreement with each other and with the results of previous investigators. Experimental results on the possibility of controlling chaos in the modified Chua's oscillator by the inherent feedback mechanism are also reported.

Power consumption of synchronous sequential circuits can be reduced by careful encoding of the states of the circuit. The idea is to reduce the average number of bit changes per state transition by finding an optimal state assignment. This state assignment problem is NP-hard, and existing techniques rely mainly on heuristic-based methods. The primary goal of this work is to assess the suitability of using complete advanced Boolean Satisfiability and Integer Linear Programming (ILP) methods in finding an optimized solution. We formulate the problem as a 0-1 ILP instance with power minimization being the objective. Using generic and commercial solvers, the proposed approach was tested on sample circuits from the MCNC benchmark suite. Furthermore, in an effort to accelerate the search process, circuits were checked for symmetries and symmetry breaking predicates were added whenever applicable. The experimental results provide a pragmatic insight into the problem and basis for further exploration.

An isolated high step-up DC-DC converter with a continuous input current is proposed. The proposed converter consists of two converter cells — a boost converter cell at the input stage for a low input current ripple and a DC-DC converter cell for high voltage gain. Zero-voltage-switching of power switches are achieved and the leakage inductance of the transformer alleviates the reverse-recovery problems of the output diodes. Therefore, the proposed converter achieves high efficiency. Detailed analysis and design of the proposed converter are carried out. A prototype of the proposed converter is developed, and its experimental results are presented for validation.

In this paper, we design and implement an integrated circuit system for contactless interface transmission to conform the transfer protocol of ISO/IEC 14443-2 Type B. The system consists of two major parts, interrogator and transponder, for magnetic power and data transmission. The power and data can synchronously be transferred from the interrogator to the transponder with 10% amplitude shift keying modulation of mixing both carrier 13.56 MHz and data rate 106 Kbps. Another data can be backward to the interrogator from the transponder with the mixed binary phase shift keying modulation. Simulation results to the whole chip based on TSMC 0.35 μm CMOS process have approved using HSPICE.

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄, Al₂O₃, HfO₂. The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1 V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of ±0.5 V.