Journal of Circuits, Systems and Computers

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard.

Due to the regularity of implementation, multiplexers are widely used in VLSI circuit synthesis. This paper proposes a technique for decomposing a function into 2-to-1 multiplexers performing area-power tradeoff. To the best of our knowledge this is the first ever effort to incorporate leakage into power calculation for multiplexer-based decomposition. With respect to an initial ROBDD (reduced ordered binary decision diagram)-based representation of the function, the scheme shows more than 30% reduction in area, leakage and switching for the LGSynth91 benchmarks without performance degradation. It also enumerates the trade-offs present in the solution space for different weights associated with these three quantities.

Despite excellent high frequency and high speed performance, current-feedback operational amplifiers (CFOAs) generally exhibit poor common-mode rejection (CMRR) properties, which limit their utility [Analogue IC design: The current–mode approach, IEE Circuits and Systems Series, Peter peregrinus, 1990]. A novel current feedback operational amplifier (CFOA) with improved performance is presented. The proposed CFOA has a new current-cell [Novel current-feedback operational amplifier Design Based on a floating circuit technique, IEE Colloquium on Analogue Signal Processing, 1998], to bias the entire circuit, which achieves an incremental output resistance twice that of the well-known "Wilson" circuit. Simulation results of this new CFOA architecture indicate that the amplifier exhibits performance characteristics superior to those obtained with an established input architecture: in particular, the CMRR (common-mode rejection ratio) is 91 dB, and the d.c. offset voltage less than 26 μV.

A new, self-biasing, differential pair-based and high performance CMOS CCII circuit is proposed which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuit has high voltage swings on ports X and Y, very low equivalent impedance on port X, high equivalent impedances on ports Y and Z and also wideband voltage and current transfer ratios. The noise analysis of the proposed CCII circuit is studied. Input referred noise voltage at high impedance port Y and input referred noise current at low impedance port X are obtained to form the noise model. Some filter circuits are selected from the literature and their noise comparisons are performed. It is shown that the noise values can differ greatly even though the filter circuits or the passive element values are identical.

Reliability analysis using error probabilities for combinational logic circuits has been investigated widely in the literature. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis is developed. A Monte Carlo method-based reliability analysis is introduced for sequential circuits, which is used for first method validation. Experimental results demonstrate good accuracy of the method.

An important part of the integrated circuit design process is the channel routing stage, which determines how to interconnect components that are arranged in sets of rows. The channel routing problem has been shown to be NP-complete, thus this problem is often solved using genetic algorithms. The traditional objective for most channel routers is to minimize total area required to complete routing. However, another important objective is to minimize signal propagation delays in the circuit. This paper describes the development of a genetic channel routing algorithm that uses a Pareto-optimal approach to accommodate both objectives. When compared to the traditional channel routing approach, the new channel router produced layouts with decreased signal delay, while still minimizing routing area.

A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advantages of using carbon-based transistors in digital designs over conventional silicon technology. The proposed circuit can be applied in ultra low power and very high speed applications.

In this paper, we present a new method for the modeling and characterization of oscillator circuit with a Van Der Pol (VDP) model using parameter identification. We also discussed and investigated the problem of estimation in nonlinear system based on time domain data. The approach is based on an appropriate state space representation of Van der Pol oscillator that allows an optimal parameter estimation. Using sampled output voltage signal, model parameters are obtained by an iterative identification algorithm based on Output Error method. Normalization issues are fixed by an appropriate transformation allowing a quickly global minimum search. Finally, the proposed estimation method is tested and validated using simulation data from a 1 GHz oscillator circuit in GaAs technology.

In a recent paper published in this journal, Soliman presented the methods of transformation of grounded inductors to floating inductors using operational floating amplifiers and floating second generation current conveyors. The purpose of this note is to bring on record the present author's earlier works on the same topic published about 24 years back which are closely related to the work reported in Soliman's paper but have not been cited therein.

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

This paper presents a novel low power consumption, low phase noise, and high tuning range CMOS cross-coupled voltage-controlled oscillator (VCO). Using common mode double-pseudo-resistance technique in the proposed circuit leads to low power dissipation without degrading the phase noise. Additionally, band-switching capacitor array is employed in order to increase the tuning range. The schematic circuit of the proposed VCO is simulated in 0.18 μm 1P6M CMOS process and simulation results show high efficiency of the proposed circuit. The overall tuning frequency range is from 1.7 GHz to 3.18 GHz (59%) with tuning voltage variation range from 0 V to 1.5 V. The proposed VCO circuit has phase noise of -102.6 and -124.3 dBc/Hz at 100 KHz and 1 MHz offset frequency from the carrier, respectively, while consumes 1.98 mW power at 1.5 V supply voltage.

With reference to an architecture for the full integration of a 60 GHz receiver in embedded systems with wireless gigabit connectivity, the paper presents the design of key building blocks such as: on-chip antenna, low noise amplifier (LNA) and a time-interleaved fast A/D converter (ADC) with AMBA AXI interface towards the digital baseband part. With respect to the state of the art the co-design of the on-chip antenna with the LNA, and the fast ADC architecture realized as a time-interleaved array of threshold-configuring SAR channels, represent new solutions optimized in terms of power consumption. Complexity and performance results in a 65-nm CMOS SOI technology, suitable also for digital systems integration, are presented. The performance and complexity results of the designed antenna, LNA and ADC are integrated in a system level simulator with those obtained by adopting known solutions for other receiver blocks (mixer, IF and baseband amplifiers and filters, frequency synthesizer) thus estimating the performance achievable with a whole 60 GHz receiver and digitization sub-system macrocell. The system-level estimated performances confirm the feasibility of a full-integrated receiver supporting short-range High Definition (HD) connectivity of several Gb/s with a Signal-to-Noise-Ratio compliant with WiGig and Wireless HD new standardization initiatives.

This paper presents two new high-order OTA-C universal filters. The first proposed filter structure employs n + 3 operational transconductance amplifiers (OTAs) and n grounded capacitors, which can realize nth-order multiple-mode (including voltage, current, transadmittance, and transimpedance modes) universal filtering responses (lowpass, highpass, bandpass, bandreject, and allpass) from the same topology. Since the OTA has high input and output impedances, it is very suitable for transadmittance-mode circuit applications. Therefore, a new high-order transadmittance-mode OTA-C universal filter structure using the minimum components is introduced. The second proposed filter structure uses only n + 1 OTAs and n grounded capacitors, which are the minimum components necessary for realizing nth-order transadmittance-mode universal filtering responses (lowpass, highpass, bandpass, bandreject, and allpass) from the same topology. This represents the attractive feature from chip area and power consumption point of view. Moreover, the two new OTA-C universal filters still enjoy many important advantages: no need of extra inverting or double-type amplifiers for special input signals, using only n grounded capacitors, no need of any resistors, cascadably connecting the former voltage-mode stage and the latter current-mode stage, and low sensitivity performance. H-Spice simulations with TSMC 0.35 μm process and ±1.65 V supply voltages are included and confirm the theoretical predictions.