Journal of Circuits, Systems and Computers

The configuration with electronic tunable characteristics that can work in mixed mode may be useful from IC realization viewpoint and application adaptability. This paper proposes an electronically tunable mixed mode universal filter based on multiple output current controlled current conveyor (MOCCCII) and this single topology without any alteration can be used in all four modes i.e., voltage (VM), current (CM), transimpedance (TIM) and transadmittance (TAM). The architecture uses four MOCCCIIs and two grounded capacitors; and can realize universal filter functions — low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) for all four modes. Moreover the input impedance is high and output impedance is low for voltage signal and vice-versa for current signal, hence the proposed topology is suitable for cascading for all four modes. The workability of the proposed circuit has been verified via SPICE simulations using AMS 0.35 μm CMOS technology.

This paper presents two new first-order voltage-mode (VM) cascadable all-pass (AP) sections, employing two differential voltage current conveyors (DVCCs) and three grounded passive components. Both circuits possess high input and low output impedance, which makes them easily cascadable. Non-ideality aspects and parasitic effects are also studied. As an application, a quadrature oscillator is designed using the proposed circuit. The proposed circuits are verified through PSPICE simulations using 0.5 μm CMOS parameters.

A two-loop control has been designed for a boost converter. An internal sliding-mode control loop forces the converter inductor current to track the reference established by H_∞ control of the output voltage in an outer loop. The outer H_∞ controller is designed through loop shaping concepts. A practical design approach that aims at systematizing the procedure for the selection of inner sliding mode control parameters is also presented. The closed loop characteristics of a typical low-power boost converter with the proposed dual loop controller implemented in the actual switched model is validated through computer simulation. The proposed controller is found to be superior due to its low distortion property, good regulating performance and insensitivity to load variations. Finally, the validity and effectiveness of the control schemes are verified through hardware experiments.

This paper aims to use the concept of energy factor and its associated concepts to analyze high-order converters, such as Cuk, Sepic and Zeta converters. The maximum variation of energy factor (MVEF) of high-order converters exhibits particular characteristic which is different from that of second order converters. To carry out the analysis based on MVEF, boundary conditions for the high-order converters should be restudied. There are new boundary conditions that are derived by analyzing the energy factor. Through the research in this paper, it can be concluded that the MVEF can reveal the amount of energy storage and impact the efficiency of high-order converters. Experimental results have confirmed that the MVEF and efficiency are correlated. MVEF can be a preferred index for DC-DC converters including high-order converters.

For the requirement of power management controller chips, a wide supply range bandgap voltage reference circuit is presented. The preregulated circuit based on the regulation characteristic of zener diode extends the supply range and increases power supply rejection ratio (PSRR). Compensated by the base-emitter voltage (V_BE) linearization technique, the temperature stability of the bandgap circuit is improved further. The proposed circuit is implemented in a 0.4 μm bipolar CMOS DMOS (BCD) process and Spice simulation has been done for validation. The results of simulation and test show that the supply range of this circuit can reach 7.2 V to 40 V and 159 μV/V of supply voltage dependence; the temperature coefficient is just 3.5 ppm/°C over a wide temperature of -40°C to 125°C and PSRR is up to -94 dB at 1 kHz. For the perfective performance, this circuit can be used in wide temperature and wide supply range integrated circuit design.

The paper presents a bandgap voltage reference (BGR) implemented in TSMC 0.25 μm BCD technology for an automotive application. To withstand a car's battery large voltage variations, from 5 V to 40 V, the circuit features an embedded pseudo-regulator providing a stable bias current for the bandgap core. High-voltage (HV) MOS count has been kept low thus allowing the design of a compact BGR with an area of 0.118 mm². The BGR has been designed to operate in automotive extended temperature range (-40°C to 150°C) and it provides a stable voltage of 1.21 V, which is also used as reference for a cascade 3.7 V linear regulator. Measurements carried on fabricated IC samples prove the effectiveness of the BGR design in terms of supported input voltage variations and operating temperature range, temperature drift, line regulation and PSRR performance.

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2ⁿ-1, 2ⁿ + 1, 2²ⁿ + 1, 2ⁿ} that only requires modulo 2⁴ⁿ - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 2⁴ⁿ - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

In this paper, a new current-mode (CM) circuit for realizing all of the first-order filter responses is suggested. The proposed configuration contains low number of components, only two NMOS transistors both operating in saturation region, two capacitors and two resistors. Major advantages of the presented circuit are low voltage, low noise and high linearity. The proposed filter circuit can simultaneously provide both inverting and non-inverting first-order low-pass, high-pass and all-pass filter responses. Computer simulation results achieved through SPICE tool and experimental results are given as examples to demonstrate performance and effectiveness of the proposed topology.

In this paper, a new current-mode second-order square-root-domain general notch filter is proposed. The design is based on the state-space synthesis method with two subcircuit; square-root and squarer/divider circuits. In the circuit, the input and the output values, and dominant variables are all currents. Only MOS transistors and grounded capacitors are required to realize the filter circuit. Three cases of the second-order notch filter were obtained. The regular notch was obtained when ω_n = ω_p, the lowpass notch was obtained when ω_n > ω_p, and the highpass notch was obtained when ω_n < ω_p. The center frequency, and the notch frequency of the filter can be electronically tuned by changing external currents. Time and frequency domain simulations are performed using PSPICE program for the filter to verify the theory and to show the performance of it. For this purpose, the filter is simulated by using TSMC 0.35 μm Level 3 CMOS process parameters.

Monotonic errors cause severe errors and are inherent in several A/D Converter (ADC) architectures. Moreover, several error correcting and ADC output processing methods require a monotonic behavior for a successful operation. Based on the features of asynchronous ADCs, an architecture for the elimination of monotonic errors is presented. This monotonic error correcting module is connected at the output of an ADC and does not require any modification in its internal circuits. It controls an output buffering stage that discards output codes with monotonic errors and this correcting procedure is triggered by changes in specific output bits of the ADC. Simulation results show an improvement by 8 dB or 25% maximum, in the signal-to-noise and distortion ratio (SNDR) of an 8-bit ADC if this monotonic error elimination method is used alone and a further improvement by 1–5 dB if it is combined with a post processing method developed by the authors. Similar improvement can also be achieved in several other architectures like Subrange or Folding ADCs that operate in relatively high oversampling ratio and suffer from monotonic errors with specific features.

A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 μm CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.

In this paper, we propose an effective framework to automatically segment hard exudates (HEs) in fundus images. Our framework is based on a coarse-to-fine strategy, as we first get a coarse result allowed of some negative samples, then eliminate the negative samples step by step. In our framework, we make the most of the multi-channel information by employing a boosted soft segmentation algorithm. Additionally, we develop a multi-scale background subtraction method to obtain the coarse segmentation result. After subtracting the optical disc (OD) region from the coarse result, the HEs are extracted by a SVM classifier. The main contributions of this paper are: (1) propose an efficient and robust framework for automatic HEs segmentation; (2) present a boosted soft segmentation algorithm to combine multi-channel information; (3) employ a double ring filter to segment and adjust the OD region. We perform our experiments on the pubic DIARETDB1 dateset, which consists of 89 fundus images. The performance of our algorithm is assessed on both lesion-based criterion and image-based criterion. Our experimental results show that the proposed algorithm is very effective and robust.

A current source circuit for high-resolution CMOS image sensors is introduced in this paper, which can provide a stable current with immunity from IR-drop along the power and ground wires. In the circuit, two pre-charged floating capacitors controlled by two-phase non-overlap clock are connected between the gate and source of a MOS transistor alternately to maintain a constant V_GS of the MOS transistor. In this way, the current flowing through the MOS transistor will be stable and has nothing to do with power level. The post simulation results show that the current supplied by the proposed circuit decreases only by 1.6% when the voltage of the power supply decreases by 30%. The simulations have proved that the proposed circuit can improve the performance of high-resolution CMOS image sensors.

This paper presents a versatile universal current-mode and transresistance-mode biquadratic filter using only two multiple outputs second-generation current conveyors (MOCCIIs), two grounded capacitors, and three grounded resistors. The proposed configuration can realize all five standard filtering functions from one current-output terminal and one voltage-output terminal, and also provide all these filtering functions from different current-output and voltage-output terminals without changing the filter topology. Moreover, the proposed biquad filter still achieves many advantages like the employment of all grounded passive components, and the minimum number of active component counts, in addition to having no need of inverting-type input signals or double-type input signals for the use of special input signals, high output impedance and low sensitivity performance. H-Spice simulation results confirm the theory.