Journal of Circuits, Systems and Computers

This paper presents a selective survey of finite difference time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modifications and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the significant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm² active area in a 0.18 μm CMOS technology.

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

In cognitive radio ad hoc networks, the opportunistic access of vacant wireless channel opens a new frontier for efficient spectrum utilization as in many situations, a wide range of spectrum is not even partially utilized by the license owners (primary users, PUs). While the idea seems to be lucrative for spectrum hungry users without licenses, a natural competition between potential stake holders arises, which needs to be regulated in order to efficiently utilize available resources and avoid chaos. With the introduction of unlicensed users in licensed bands, the operations and interests of PUs need to be protected, hence the spectrum owners are given an advantage and control over the multiple access policy (a leader-follower scenario). In this work, we address the problems in spectrum access and channel selection equilibrium in a leader (PU)-follower (secondary user, SU) setup. In contrast to previous game formulations that lack efficient power and pricing schemes, we present a cooperative Stackelberg potential game for cognitive players. A dynamic cost function is articulated to induce awareness in players to mitigate the effects of selfish choices in spectrum access while at the same time steer the distributed network towards achieving Nash equilibrium. The proposed scheme is mutually beneficial for all players and focuses on improving the network performance and power efficiency. We design the network potential function such that the nodes have performance based incentives to cooperate and achieve a Nash equilibrium solution for efficient channel acquisition and capacity. Simulation results show fast convergence in channel selection strategies and increase in capacity for the entire network.

An architecture proof-of-concept which adapts the throughput datapath based on the anticipation of computational demand in dynamic environments is demonstrated and evaluated for a motion estimation (ME) engine. The input signal characteristics are exploited to anticipate the time varying computational complexity as well as to instantiate dynamic replicas (DRs) to realize fault-resilience. The scheme employs amorphous processing elements (APEs) which either perform as active elements (AEs) to maintain quality/throughput, serve as DRs to increase reliability levels, or hibernate passively as reconfigurable slack (RS) available to other tasks.

Experimental results from a hardware platform for field programmable gate array (FPGA)-based video encoding demonstrate power efficiency and fault-tolerance of the ME engine. A significant reduction in power consumption is achieved ranging from 83% for low-motion-activity scene's to 12.5% for high motion activity video scenes. The scenes motion activity is utilized to improve redundancy for the purpose of priority based diagnosis of the computing modules. In addition, a graceful degradation strategy is developed to recover from hard errors by adapting the search range of candidate motion vectors (MVs). This adaptive hardware scheme is shown to automatically demote the faulty resources in FPGA devices based on streaming performance.

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

The increasing complexity of cryptographic devices requires fast simulation environment in order to test their security against fault attacks. SystemC is one promising candidate in Electronic System Level that allows models to reach higher simulation speed. However in order to enable both fault injection and detection inside a SystemC cryptographic models, its code modification is mandatory. Aspect-Oriented Programming (AOP), which is a new programming paradigm, can be used to test the robustness of the cryptographic models without any code modifications. This may replace real cryptanalysis schemes. In this paper, we present a new methodology to simulate the security fault attacks of cryptographic systems at the Electronic System Level. A fault injection/detection environment is proposed to test the resistance of cryptographic SystemC models against fault injection attacks. The fault injection technique into cryptographic SystemC models is performed using weaving faults by AspectC++ as an AOP programming language. We validate our methodology with two scenarios applied to a SystemC Advanced Encryption Standard case study: the first is related to the impact of the AOP on fault detection capabilities, while the second refers to the impact of the AOP on simulation time and size of the executable files. Simulation results show that this methodology can evaluate perfectly the robustness of a cryptographic design against fault injection attacks. They show that the impact of AOP on simulation time is not significant.

Growing concerns on the energy crisis impose great challenges in development and deployment of the smart grid technologies into the existing electrical power system. A key enabling technology in smart grid is distributed generation, which refers to the technology that power generating sources are located in a highly distributed fashion and each customer is both a consumer and a producer for energy. An important optimization problem in distributed generation design is the insertion of distributed generators (DGs), which are often renewable resources exploiting e.g., photovoltaic, hydro, wind, ocean energy.

In this paper, a new power loss filtering based sensitivity guided cross entropy (CE) algorithm is proposed for the distributed generator insertion problem. This algorithm is based on the advanced CE optimization technique which exploits the idea of importance sampling in performing optimization. Our experimental results demonstrate that on large distribution networks, our algorithm can largely reduce (up to 179.3%) power loss comparing to a state-of-the-art sensitivity guided greedy algorithm with small runtime overhead. In addition, our algorithm runs about 5× faster than the classical CE algorithm due to the integration of power loss filtering and sensitivity optimization. Moreover, all existing techniques only test on very small distribution systems (usually with < 50 nodes) while our experiments are performed on the distribution networks with up to 5000 nodes, which matches the realistic setup. These demonstrate the practicality of the proposed algorithm.

We present an unified explanation of the transconductance-to-drain current (g_m/I_D)-based noise analysis in this paper. We show that both thermal noise coefficient (γ) and device noise corner frequency (f_co) are dependent on the g_m/I_D of a transistor. We derive expressions to demonstrate the relationship between the normalized noise power spectral density technique and the technique based on γ and f_co. We conclude this letter with examples to demonstrate the practical implication of our study. Our results show that while both techniques discussed in this letter can be used to compute noise numerically, using γ and f_co to separate thermal noise from flicker noise provides additional insight for optimizing noise.

It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing algorithm in terms of hardware cost and the design time is also saved.

It is generally difficult to effectively eliminate intentional multiple component interference in any communication systems mainly because of the difficulties in accurately estimating the parameters of interference particularly in low signal-to-noise ratio (SNR) environments. This paper proposes effective methods of adaptive interference suppression based on Lv distribution (AISL) for direct sequence spread spectrum (DSSS) communications. Since the recently reported Lv distribution (LVD) provides better concentration of signal energy in the domain of frequency-chirp rate than other reported methods, it achieves performance improvement on estimating the parameters containing multiple linear frequency modulated (LFM) signals. With the desirable properties of the LVD, the proposed interference suppression methods are able to excise interference of multiple components. The proposed methods firstly examine if the received signal is interfered by using a high-order statistics, known as skewness, to measure the distribution concentration of the received signal in the LVD domain. Then the interference excision process is employed only when the interference is present. Two methods, i.e., AISL-I based on the concept of interference cancellation and AISL-II based on phase cancellation and filtering, are investigated. The merits of these methods are analyzed and compared in terms of bit error rates (BERs). Results of Monte Carlo experiments are also presented to show the effectiveness of suppressing interference by the proposed methods.

This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

A novel coplanar waveguide (CPW) fed circular slot antennas are proposed for industrial, scientific and medical (ISM) band (2.4–2.48 GHz) applications. To make the designed antenna suitable for implantation, it is embedded in biocompatible Al2O3 ceramic substrate. The antenna was simulated by immersing it in a phantom liquid, imitating the electrical properties of the human muscle tissue. A study of the sensitivity of the antenna performance as a function of the dielectric parameters of the environment in which it is immersed was performed. Simulations in various dimensions state demonstrate that the antenna covers the complete ISM band. The demonstration among the design EM characteristics of the antenna is presented by current distributions.

A class of singular nonlinear systems with set-valued mappings are studied in this paper. Criteria are given based on the Lyapunov function to check the absolute stability of the systems, then the results are extended to the time delay systems and the time delay systems with uncertainty. Three examples are simulated to show the effectiveness of the proposed stability conditions.

In this paper, a high speed residue to binary converter for three moduli set {2ⁿ - 1, 2ⁿ + 1, 2ⁿ} is presented in this paper, which uses two-part RNS and is based on mixed radix conversion (MRC). By using two-part RNS, the number of modulus in each part decreases; therefore the complexity of reverse converter is reduced. Also, the architecture of the proposed converter is based on subtractors and Multiplexers which are suitable for VLSI implementation. Reducing the number of modulus and simplifying the structure of the proposed converter lead to improvement of the latest presented converter in terms of area and delay. In order to obtain an accurate comparison, the proposed converter and the fastest designs were implemented on Xilinx 12.1 FPGA simulator, area and delay of each converter was measured for various word widths up to 64-bit. As the results indicated the novel proposed method has better Area and conversion time comparing to the previous designs.