Journal of Circuits, Systems and Computers

A wideband CMOS LC tank voltage-controlled oscillator (VCO) with low phase noise variations and a linearized gain has been designed using a new binary-weighted switched-capacitor and digitally-controlled varactor bank. The novel design has the advantages of more linear VCO frequency tuning, lower phase noise and reduced gain to variations in supply voltage. The proposed VCO has been designed using UMC 90-nm, 6-metal CMOS technology and features phase noise variation of less than 4.9 dBc/Hz. The VCO operates from 3.45 to 6.55 GHz, with phase noise of -133.4 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.3 dBc/Hz, less than 41 dBm spurious harmonics, and a total VCO core current consumption of 1.18 mA from a 3.3 V voltage supply. To the authors' knowledge, this is the lowest phase noise variation ever reported.

The Standard Test Interface Language (STIL) is the de-facto standard for transferring test data between the test generation environment and the test equipment. STIL's flexibility and extensibility facilitates its use as the sole input language for automatic test-pattern generation (ATPG). However, STIL format is complex and does not provide support for algorithmic interactive testing which necessitate the use of additional programming languages to do that. In this paper, we propose a new Test Definition Language for Integrated Circuits (TDLIC) based on the Extensible Markup Language (XML). TDLIC is a description language for defining tests of digital ICs in a precise and reusable form. The proposed TDLIC provides a common platform for specifying test data as well as complex test procedures. A case study that includes a validation platform is used to show the full capabilities of TDLIC. The validation platform is an FPGA-based system that emulates the automatic test equipment and a prototype IC with four circuits to be tested.

A method to reduce the side effects of dual-line timed address-event (TAE) vision system is proposed in this paper. The side effects include edge discontinuity and the natural insensitivity to object edges in the motion direction. X-event, a kind of artificial event is introduced to represent light intensity difference perpendicular to the motion direction of the target object. New timestamps are attached to the raw TAE data to adjust temporary resolution to the same order of magnitude with the vertical axis in the TAE representation. After removing noisy and redundant events, designed templates are used to generate X-events to renovate broken lines and reproduce perpendicular edges. It is a real-time process which is unnecessary to wait for the collection of all the raw TAE data. A behavioral model of a 2 × 256 TAE vision sensor is established in Matlab, and X-events Generation block is realized in FPGA. Experimental results show that the proposed method can patch the TAE representation effectively to obtain a one-pixel-wide, precise, closed and connected contour.

Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new functional unit called the calculation and anticipation (C&A) unit is presented for the IEEE 754 standard floating-point adder (FPA) that is the most important and frequently used calculation part for both modern CPUs and GPUs. C&A unit parallelize rounding step and readjustment step, which are known as the time-consuming steps for floating-point addition with significand addition. Therefore it reduces FPA critical path delay enormously, and even more decreases a little FPA area occupation. The synthesis results show that the double-precision FPA with C&A unit takes about 17.17% improvement in the critical path delay, while saves about 8.32% area than the conventional one. It takes 5.90% advantage in area and 19.58% improvement in the worst case delay than the double-precision FPA from the Open Core module "fpu_double" (rev 14 2010-02-13) synthesized in the same 0.13-μm CMOS bulk. Furthermore, comparing with the two-path double-precision FPA synthesized using LSI Logic's gflxp 0.11-μm CMOS library, it takes about 4.30% advantage in the critical path delay, and saves almost one-third area in the number of the individual cells.

A detailed controller design for indirect constant power regulation of high intensity discharge (HID) electronic ballast and the experimental implementation of an adaptive passivity-based constant power (PBC) controller has been extensively studied through simulation and the findings are reported in this paper. An indirect method to regulate the inductor current to ensure the lamp constant output power is proposed in order to overcome the difficulties in measuring the output power of the HID ballast. The controller is derived using passivity theory which guarantees global stability and asymptotic convergence of all state errors. The simulation and controller design are based on an average model using the Euler–Lagrange (EL) equations of the system. As the lamp resistance will inevitably change with ageing, an adaptive method is used to compensate for the lamp performance as the lamp ages. This equips the controller the power to adapt to load variations and there is no need to tune the design parameters values each time manually. Another interconnection and damping assignment (IDA)-PBC method is analyzed and simulation results are provided for comparison. Computer simulation and hardware implementation are carried out to verify the system model and to demonstrate the controller is robust.

This paper shows the problem of possible existence of statistical self-similarity and long-range (long-term) dependencies in behavior of computer memory systems. It will be shown, that the hierarchical structure of memory and the dispersion of time constants during accessing successive levels of such a structure, lead to "memory effect" and self-similarity. These effects have not been taken into account so far in computer systems design, management and description. A few methods were used to calculate the Hurst H coefficient, which reflects the statistical self-similarity in time series and the d parameter that represents the problem of long-range dependencies.

This paper presents a new bootstrapped switch with high speed and low nonlinear distortion. Instead of fixed voltage, the gate-to-source voltage of switch varies with input to implement first-order body effect compensation. Post-layout simulations have been done in standard 0.18-μm CMOS process at 1.8 V, and results indicate that at 200 MHz sample rate, a peak signal-to-noise-and-distortion ratio (SNDR) of 98.4 dB, spurious-free dynamic range (SFDR) of 105.7 dB and total harmonic distortion (THD) of -104.9 dB can be acquired. For input frequency up to the 60 MHz frequency, proposed structure maintains |THD| over 85 dB, SFDR better than 86 dB, respectively.

The residue theorem is a powerful tool in mathematics and signal processing, such as it is usually employed for the inverse Laplace transform and the inverse Z transform. With respect to the most commonly rational functional form in the Z transform, a theorem and a new formula for residue calculus based on the singular zero point is introduced. Then two consequences are proposed. Finally, based on the derived theorems, a new convenient algorithm for computing the inverse Z transform is presented. Applications with satisfying results indicate convenience and workability of the proposed method.

A digital controller for LED driver is presented. The controller is used in the flyback converter which works in discontinuous current mode (DCM). A comparator is adopted to shape the auxiliary winding voltage based on traditional primary side regulation (PSR). A five-states finite state machine (FSM) is designed to deal with the shaped auxiliary winding signal. The FSM extracts the system time information from the shaped signal and controls all the sequences in the whole system. To achieve high accuracy of the output current, an adaptive delay compensation scheme is adopted. A LED prototype whose typical output power is 7 W is used in both simulation and experiment to demonstrate the effectiveness of this novel digital controller. The measurement results show that the line regulation when the input ac voltage varies from 85–265 V is 3.4% and the load regulation when the load varies from 3–10 LEDs is 2.5%.

This paper presents a new nth-order elliptic filter structure with second generation current conveyor (CCII). Synthesis methodology for mixed mode odd and even order filter is proposed. The designed structure is emphasized on the basis of implementation of integrated circuit fabrication by using grounded passive components (resistors and capacitors). The proposed structure is designed for different point of interests: (i) no component constraint, (ii) the structure is compatible with equal capacitance design, which is suitable for integrated circuit fabrication, (iii) low sensitivity like LC ladder filter and (iv) nearly null group sensitivity. To validate the theory, HSPICE simulation with 0.13-μm process and BSIM level 53 model is carried with ±1.5 V power supply.

An L1 band highly integrated low noise GPS receiver in 0.18-μm CMOS is presented in this paper. The receiver adopts double conversion structure and two dynamic range control modes of variable gain amplifier (VGA) and programmable gain amplifier (PGA). The receiver includes the blocks of LNA, down-conversion mixers, band pass filter, received signal strength indicator (RSSI), VGA, PGA, 2-bit ADC, two frequency synthesizers and so on. The LNA adopts source inductive degeneration technique to achieve good noise performance, and a novel positive feedback capacitor is introduced to enhance gain. The novel gain-boosting charge pump (CP) structure acquires accurate current matching of 0.1% error which improves the output phase noise of frequency synthesizer. The measured radio performances of noise figure (NF) is only 4 dB and the maximum gain is 110 dB. The gain control range achieves 50 dB provided by PGA and VGA. The receiver occupies an area of 1.875 mm × 1.575 mm including all needed voltage reference and the 1.8 V low dropout regulator.

This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

A multifunctional system that performs synthetic aperture radar (SAR) and communication tasks is presented. The system depends on orthogonal frequency division multiplexing (OFDM) waveform shaping and multiple input multiple output (MIMO) configuration to achieve enhancement in the spectral efficiency of communication operation and provide interference rejection in SAR imaging. The SAR interval idle time is utilized to enhance the communication signal through diversity. Adaptive system features are introduced to achieve multi-user detection and improve the communication reliability, by means of space division multiple access (SDMA) and space–time block coding (STBC). Investigations of linear and nonlinear multi-user detection (MUD) techniques are provided. Moreover, a genetic algorithm-based system is developed to optimize the MUD problem and to provide near-optimal performance even for overloaded scenarios. A gain of more than 4 dB is achieved at bit error rate of 10^-2.

In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources.

In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.

This paper presents the design and simulation results for a Federal Communication Committee (FCC) complaint current starved delay line based Ultra Wide Band (UWB) Gaussian pulse transmitter, which is designed for operating in the 3.1–10.6 GHz range. The wavelet is a mono cycle Gaussian impulse wave, which is practically well suited for low cost, low power, low data rate wireless data transfer such as in wireless body area network (WBAN) applications. The transmitter operating frequency and bandwidth (BW) is controlled using a dc voltage provided at the input stage of a voltage controlled delay line (VCDL) and this aspect can be exploited for increasing the communication coverage area without compromising on the power consumption. A Gaussian wave shaping is performed for FCC compliance and the simulation has been carried out with 130 nm technology. The simulation of our design suggests an average dynamic power consumption of 1.11 mw for an energy efficiency of 14.2 pJ/pulse. The proposed IR-UWB transmitter design though a bit inferior in terms of the power efficiency, can claim superior performance with respect to tuning the BW, which is very relevant in a cognitive wireless networking scenario with other interfering signals.

Ad hoc wireless networks are self-generating and self-organizing networks consisting of mobile and static nodes, which are small and have limited power resources. In a typical setup, these nodes communicate with each other through wireless medium and may act as source, destination and/or relaying nodes. As the power of the remote nodes is depleted very quickly, it is important to have a renewable energy source to support the network operations and increase lifetime. The availability of energy from the environment is unpredictable, random and uncertain, therefore energy harvesting with appropriate management plays an important role in continuous operations of ad hoc networks. In this paper, an energy harvesting and management model is presented for ad hoc networks. Along with harvesting energy, the proposed model ensures the connectivity requirements of the network for its perpetual operation.

The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.

The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively.