Journal of Circuits, Systems and Computers

Digital filters for recursively computing the discrete Fourier transform (DFT) and estimating the frequency spectrum of sampled signals are examined, with an emphasis on magnitude-response and numerical stability. In this tutorial-style treatment, existing recursive techniques are reviewed, explained and compared within a coherent framework; some fresh insights are provided and new enhancements/modifications are proposed. It is shown that the replacement of resonators by (non-recursive) modulators in sliding DFT (SDFT) analyzers with either a finite impulse response (FIR), or an infinite impulse response (IIR), does improve performance somewhat; however, stability is not guaranteed as the cancellation of marginally stable poles by zeros is still involved. The FIR deadbeat observer is shown to be more reliable than the SDFT methods, an IIR variant is presented, and ways of fine-tuning its response are discussed. A novel technique for stabilizing IIR SDFT analyzers with a fading memory, so that all poles are inside the unit circle, is also derived. Slepian and sum-of-cosine windows are adapted to improve the frequency responses for the various FIR and IIR DFT methods.

In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and overshoot/undershoot analyses for the application of signal interconnects. The results are compared with that of the traditional Cu-based interconnects. The results show that GNR is better than Cu as far as IR drop, SSN, gate oxide reliability and hot carrier reliability are concerned. Our investigation reveals that GNR can be better than the Cu interconnects from all aspects with a multilayer GNR structure. The present graphene-based interconnect technology needs to be advanced, so that the metal–graphene contact resistance is minimized and multilayer GNR structure with large number of graphene layers is supported.

Content addressable memory (CAM) is a hardware implementation of lookup table which performs high speed search operation within a single clock cycle. Search data is compared in parallel with all the stored data and this increases switching activities as well as charging and discharging of capacitive matchlines (MLs). Here, we divide a wordline and ML into segments. For the first reported time the ML segments are precharged to different voltage levels to achieve improved energy metric. One of the segments associated with sub-ML is precharged with a low level of voltage source to reduce the power associated with ML activities. The main ML will discharge only when all the three segments match. Voltage scaling is done carefully in MLs where the switching activity is high to reduce the power consumption without degrading the search speed. A 256 $\times$ 144 bit CAM is implemented with novel CAM cells in 45-nm technology node and the post-layout simulation is performed. The averaged energy metric is 0.12 fJ/search/bit for 625 Monte Carlo (MC) simulations with process variations.

Barrel shifter is an integral component of processor datapaths in computing systems since it can shift and rotate multiple bits in a single cycle. Furthermore, reversible logic has applications in emerging computing paradigms such as quantum computing, quantum dot cellular automata, optical computing, etc. In this work, we propose efficient methodologies for designing reversible barrel shifters. The proposed methodologies are designed using Fredkin gate and Feynman gate (FG). The Fredkin gate is used because it can implement a 2:1 MUX with minimum quantum cost, minimum number of ancilla inputs and garbage outputs, and the Feynman gate is used to avoid a fanout since a fanout is not allowed in reversible logic. In the existing literature, design methodologies are limited to the design of a ($n,k$) reversible left rotator that can only perform the left rotate operation. This work explores the other primary functionalities of a reversible barrel shifter such as the design of a reversible: (i) logical right shifter, (ii) universal right shifter that supports logical right shifter, arithmetic right shifter and right rotate operation, (iii) bidirectional logical shifter and (iv) universal bidirectional shifter that supports bidirectional logical and arithmetic shifter and rotate operations. The other types of reversible barrel shifters can also be easily designed by making minor modifications in the proposed methodologies. The proposed design methodologies are generic in nature and can be implemented using any barrel shifter of ($n,k$) size, where n and k are the number of data bits and shift value, respectively. In order to minimize the number of ancilla inputs and garbage outputs, strategies such as the implementation of an n number of 2:1 MUXes as a chain of n Fredkin gates and the mapping of the two different 2:1 MUXes that are controlled by a common control signal but having the swapped controlled signals on a single Fredkin gate, are utilized. The design methodologies are evaluated in terms of the number of garbage outputs, the number of ancilla inputs and quantum cost. For a ($n,k$) reversible barrel shifter, the relations between the varying values of n and k and their impact on the number of garbage outputs, the number of ancilla inputs and quantum cost are also established to help the designers in choosing an efficient barrel shifter according to their design needs.

In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Different reforms are performed in multiplier architecture. In the first step of multiplier operator, a novel radix-16 modified Booth encoder is presented which reduces the number of partial products efficiently. In this research, we present a new algorithm for partial product reduction in multiplication operations. The algorithm is based on the implementation of compressor elements by means of carry network. The structure of these compressors into reduction trees takes advantage of the modified Wallace tree for integration of adder cells and provides an alternative to conventional operator methods. We show several reduction techniques that illustrate the proposed method and describe carry-skip examples that combine dynamic CMOS with classic conventional compressors in order to modify each scheme. In network multiplier, a novel low power high-speed adder cell is presented which uses 14 transistors in its structure. Critical path is minimized to reduce latency in whole operator architecture. Final adder of multiplier uses an optimized carry hybrid adder. The presented final adder network uses dynamic CMOS technology. It sums two final operands in a very efficient way, which has significant effect in operator structure. Presented multiplier reduces latency by 12%, decreases transistor count by 8% and modifies noise problem in an efficient way in comparison with other structures.

The use of quantum-dot cellular automata (QCA) technology for the design of logic circuits has shown to increase data transfer rates up to 2 THz. In QCA technology, circuits are designed to have an ultra-small feature size as well as ultra-low power consumption. Grain-128 is one of the best stream ciphers in the final list of the eSTREAM project. In this paper, we have designed and simulated the main blocks of this algorithm including XOR gate, linear-feedback shift register (LFSR) and nonlinear-feedback shift register (NLFSR) using QCA technology. The designs of these blocks using the QCA Designer simulator are given and the main factors such as area, complexity and delay are estimated. Furthermore, ModelSim software is used to simulate HDLQ model of the QCA Grain-128 stream cipher algorithm. The results indicate that the main parameters of the proposed Grain-128, such as area and throughput, are improved as well.

A 3GHz class of an E_F and ${\mathrm{\Psi }}_{\mathrm{\text{U}}}$ shaped Microstrip Patch Antennas (MPAs) designed, simulated and fabricated has been presented in this paper. These simulated designs with appropriate parameters are implemented on the fabrication prototypes which have been validated with help of Agilent Microwave Analyzer (N99917A). These proposed MPAs and dielectric equivalent human breast model that have been validated using the different dielectric strengths of coupling mediums are presented. These MPAs and dielectric equivalent human breast model have been validated using the existing Debye test bed. The coverage and vector dimension of tumor tissues have been detected using the Monostatic radar approach in the E_F and ${\mathrm{\Psi }}_{\mathrm{\text{U}}}$ shaped MPAs-based existing Debye test bed setups. This paper conclude that Fractional Bandwidth (FBW) of E_F shaped MPA is 26.79% greater than ${\mathrm{\Psi }}_{\mathrm{\text{U}}}$ shaped MPA of 21.67%. Hence, the E_F and ${\mathrm{\Psi }}_{\mathrm{\text{U}}}$ shaped MPAs prototypes are suitable for breast cancer diagnosis systems. The prototypes’ depth, coverage and vector dimensions are presented in this paper.

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). When input signal frequency is very high, timing skews have significant effect on distortion. Therefore, a new timing skew calibration method is proposed in this paper. This method is based on the truth that timing skews are related to the product of the outputs of sub-ADCs. After timing skews are estimated, the digital controlled delay elements (DCDE) in ADC and phase locked loop (PLL) are utilized to calibrate timing skews. No auxiliary circuit and digital filter are needed for this calibration method. Simulation results show that the proposed method can estimate timing skew accurately. It is also proved that an accurate estimation can be obtained even the signal to noise ratio (SNR) of input signal is 20dB. The proposed method is employed to calibrate timing skews in a 16-channel TIADC-based 20GSPS digital storage oscilloscope (DSO). The experiment results demonstrate the usefulness of the proposed method. We can see that after timing skews are calibrated, the spectrum spurs have been effectively eliminated.

Digital channelizer is used to separate the sub-band signals contained within a wideband intermediate frequency (IF) received signal. This paper presents a structure of digital channelizer which is built upon estimation of the sub-band signal number. The proposed structure is designed by employing nonuniform filter banks (NUFBs), which are implemented by merging the adjacent sub-branches of the perfect reconstruction (PR) cosine modulated filter banks (CMFBs). Using source number estimation algorithm, the estimated value of sub-band number can be obtained. By energy detection, the energy characteristic of the analysis filter banks (AFBs) can be acquired and another value of sub-band number is calculated. Comparing the estimated value and the calculated one, we can evaluate whether the design of the AFB is suitable for the received signal. The structure of digital channelizer proposed by this paper provides a potential way to channelize the unknown signal and suggests a solution for the dynamic channelizaiton. A design example is also presented to demonstrate the feasibility and simplicity of this method.

Current works on generation of combinational logic circuits (CLC) using evolutionary algorithms (EA) propose solutions using field-programmable gate array (FPGA) to accelerate the process of combinational circuit simulation, a step needed in order to evaluate the level of correctness of each individual circuit. However, the current works fail to separate the two distinct problems: the EA and the circuit simulator. The insistence of treating both problem as a single one results in works that fail to address either properly, restricting solutions to simple circuits and to topologically restrictive circuit simulators, while providing very limited data on the results. In this work, we address the circuit simulator problem exclusively, where we propose an architecture for fast simulation of n-LUT CLC of arbitrary topology. The proposed architecture is modular and makes no assumptions on the specific EA to be used with. We provide detailed performance results for varying circuit dimensions, and those results show that our architecture is able to surpass other works both in terms of performance and topological flexibility.

A versatile low-voltage CMOS circuit with a trapezoidal transconductance characteristic and independently programmable slope, height and horizontal position is designed in 0.18$\mu$m standard CMOS technology. The proposed circuit is constructed from combination of two linearization methods to enhance the linearity in low voltage applications. A $-$118dB THD was obtained for a 400mV peak to peak differential input voltage at 125KHz. Simulation results using HSPICE that verify the functionality of circuit with 1.5V supply are presented. The total power consumption is only 120$\mu$W. The circuit can find application in the implementation of membership functions in analogue and mixed-signal neuro-fuzzy systems.

Electrical circuits based on linear and nonlinear modelling principles have difficulties to meet demands caused by a large amount of data generated and processed. The aim is to examine the existing models from bigeometric calculus point of view to obtain accuracy on the results. This work is an application of bigeometric Runge–Kutta (BRK4) method aiming to solve differential equations with nonzero initial condition. This type of work arises from applications where the systems are defined by ordinary differential equations such as noise, filter, audio, chaotic circuits, etc. Solutions to these types of equations are not always easy. The improvement in this work is obtained by introducing bigeometric calculus in the process of seeking a solution to differential equations. Different classes of input signals are applied as input to the system and processed to determine the accuracy of the output. The applicability is tested against the classical method called Runge–Kutta (RK4). Simulation results confirm the application of BRK4 method in electrical circuit analysis. The new method also provides better results for all types of input signals, i.e., linear, nonlinear, constant or Gaussian.

Microgrids (MGs) are small scale energy unit networks that can offer an adequate energy supply to cover local demand by incorporating renewable energy and storage technologies. The system capacity is generally between several kW to several MW. They work in terms of low voltage (LV) level or medium voltage (MV) level. They can also be connected/disconnected from main grid whenever it is necessary. This paper presents a comparison of two soft computing (SC) techniques fuzzy logic (FL)/artificial neural network (ANN) over a conventional proportional integral (PI)-based voltage frequency controllers used for improving the performance of MG under islanding mode. Microgrid is formed by using three 7.5kW, four pole, 50Hz, self-excited induction generators (SEIGs) driven by small hydro turbine feeding three-phase four-wire consumer load. The proposed topology functions excellently in maintaining phase angle, voltage and frequency (VF) regulation of the micro sources (MSs) in islanded mode as well as in resynchronization when one of the MSs is turned off due to fault or unavailability of resources. The conventional PI controller is replaced by a controller based on SC techniques, as it has disadvantages like explicit description of mathematical model, affected by variations in consumer loads and sources, thus the proposed SC techniques enhance the performance of VF controller. A comparative analysis of PI/FL/ANN controller is also carried out to highlight the superiority of AI controller. The performance of controller with proposed configuration is verified for balanced/unbalanced non-linear load. Microgrid and control schemes are simulated in MATLAB Sim Power Systems environment.

A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper. The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection NMOS transistor in series with an inductor. Together with body-biased technique and current-reused topology, the locking range of the ILFD is improved and the power consumption is reduced. The circuit is implemented in a 0.18$\mu$m standard RF CMOS process. At the incident power of 0dBm, the measured locking range of the divide-by-2 and divide-by-3 modes are from 5.37GHz to 7.68 (8.07GHz to 11.4GHz) GHz, and the core circuit without buffers consumes 3mW at the supply voltage of 1.5V. The chip only occupies $0.23\times 0.8{\mathrm{\text{mm}}}^2$ without the pads and the buffers.

Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C²NOT gate. Based on the realization of the ternary half-subtractor, we proposed the realization of a ternary full-subtractor.

When designing a system-on-chip (SOC), a network-on-chip (NOC) paradigm is the backbone of used interconnection, but in recent years, with a great improvement in silicon technology and the ability to implement billions of transistors on a wafer, it sounds that wire-based communication is not efficient any longer, therefore designers intend to replace wireless transferring data methodology instead. In the following, we show how the performance of the wireless network is improved with subnet extension. This paper focuses on the evaluation of delay and throughput which are two important factors in network proficiency. In fact, to enhance the performance of the system, we need to reduce the number of delay cycles and improve the throughput, therefore to keep balance between these two parameters, designer has to adjust the packet injection rate (PIR) in a safe margin such that it does not exceed a certain point in each state, otherwise delay is uncontrollable, thus it is required to clearly identify the take-off points. About the designer also has to be informed purpose for which the system is going to be designed. It strictly depends on whether high throughput or low delay cycle is desirable. Subnet extension is a way to achieve this target. Here, totally three networks with the number of cores 64, 512 and 1024 have been selected, respectively. The effect of subnet extension is evaluated on each one. The behavior of each network with different number of subnets and IPs is studied. Obtained results from the simulator for different ranges of PIR and subnets are significant. To emphasize, we highlight the take-off points for the delay cycles and the points which does not cross the PIR level. Performance evaluation is conducted based on flit-accurate and open source system C simulator BookSim.

Carbon nanotube field effect transistor (CNFET) is one of the promising technologies as a replacement for current CMOS technology due to its excellent electronic properties. CNFETs can be fabricated in regular structures, making them ideal for creating the repetitive architectures found in field programmable gate arrays (FPGAs). However, CNFETs face some fabrication challenges. The unwanted metallic carbon nanotubes (CNTs) are one of the major challenges in using CNFET technology for FPGAs. In this paper, we take the advantage of FPGAs programmability allowing reconfiguration around the metallic CNTs to tolerate this defect. We demonstrate a multi-stage solution to the metallic CNT problem in CNFET-based FPGAs that does not require any metallic nanotube removal of any kind. The proposed methodology consists of four consecutive stages in logic mapping process: (i) reordering of input variables, (ii) inputs complementing, (iii) adding inputs redundancy to basic logic element (BLE) and (iv) BLE lookup table (LUT) splitting. A fault simulation tool is designed to work closely with VPR, an academic FPGA CAD tool, to provide the investigation of metallic CNTs effects on CNFET-based FPGAs. Experimental results show that the proposed method can successfully map all logical nets at a cost of $4.5\times$ area overhead if the fraction of metallic CNTs is reduced to 30%.