Journal of Circuits, Systems and Computers

Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error $({\epsilon }_{max})$, normalized mean error $({\epsilon }_{mean})$ and normalized mean-square error $({\epsilon }_{mse})$ to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research.

Design methodology of a voltage-mode programmable biquadratic filter using minimum components is proposed in this paper. Multifunction second-order filter has been implemented using two first-order filter sections. The proposed biquadratic filter has been realized with operational transconductance amplifier (OTA). Cut-off frequency and $Q$-factor of the biquadratic are controlled by the transconductance of the OTAs. The proposed design technique keeps all the sensitivities to lower values. The biquadratic filter operates at high frequency. The proposed structure is transformed into a third-order multifunction filter by adding minimum component, a single capacitor. Design of higher order filter using the proposed second-order function also has been investigated. The proposed synthesis is validated with SPICE simulation in 0.13$\mu$m technology. Total harmonic distortion, output noise, corner simulations, Monte Carlo analysis due to the circuit parameter and process parameter variation have been studied.

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

In this paper, two expressions are derived for calculating the time moments and Markov parameters of continuous interval systems. The expressions presented are computationally simple and do not require inversion of denominator of the system transfer function unlike other techniques. The usefulness of expressions derived is shown with the help of Routh–Padé approximation of interval systems. The derived Routh–Padé approximants retain not only the time moments but also some Markov parameters of high-order interval system. Some improvement is also found in system approximation when these time moments/Markov parameters are used. One numerical example is included to illustrate the effectiveness and simplicity of proposed method.

This paper proposed an energy efficient adder employing multistage latency and approximate computing technology. The delay of the adder decreases after the critical path of the adder is divided into multiple short stages with series of predictors, then the approximate computing technology is exploited to make a tradeoff between output quality and energy efficiency. The proposed design is applied into discrete cosine transformation (DCT) in image processing and support vector machine (SVM) algorithm in machine learning to verify its availability, the simulation results demonstrate that the proposed approximate adder provides 25.6% power-delay-product (PDP) reduction and 2 orders of magnitude reduction in output error than the recent counterpart designs. Compared with the conventional accurate ripple carry adder (RCA) and Kogge stone adde (KSA), the proposed design presents 66.5% to 37.6% PDP reduction, at the cost of negligible output quality reduction, which are qualified as peak signal-to-noise ratio (PSNR) for DCT (decreases from 33.88dB to 33.84dB) and classification accuracy for SVM (decreases from 80.46% to 79.19%).

This paper presents design and measurement results of a DC–DC converter, intended to harvest energy from a thermo-electric generator (TEG). The prototype chip was fabricated in 130nm CMOS technology. The designed converter can extract maximum power from a TEG, without using an input capacitor ($C_{\mathrm{\text{IN}}})$ or a closed loop maximum peak power tracking circuit to regulate the input voltage ($V_{\mathrm{\text{IN}}})$. The converter uses a low voltage oscillator coupled with charge pump to directly power the auxiliary circuits; and auxiliary circuits drives two inductors in two half cycles of a clock pulse. The measurement has been performed by using a TEG, and a voltage source (50–200mV) with a series resistance of 5ohms. The result shows that the prototype can self-starts from 70mV with 5ms startup time and can work up to a minimum of 50mV; and can extract, 57.2% (at 50mV) to 65% (at 200mV), of the available power.

Leakage power reduction of an SRAM-based look-up table (LUT) in field-programmable gate array (FPGA) has been achieved in this work by implementing an efficient and dynamic power gating technique. The logic of gating is based on the theory of automatically shutting down the power supply to the inactive blocks of LUT during runtime, contrary to all previous works which involved manual intervention for the implementation of power gating. Two techniques of power gating are introduced in this work, PG1 and PG2. PG1 results in more power savings than PG2, however, PG2 has an advantage of low area overhead. Simulation has been carried out for all possible input combinations of LUT, designed in Cadence Virtuoso tool at 45nm technology. The results indicate a leakage power reduction of up to 50% in PG1 technique, with an average area overhead of 14.15%. The power savings in PG2 is up to 38%, with a minimal increase in area of 1.76%. The power bounce noise is also analyzed for the proposed techniques and reported.

Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

Wireless sensor networks (WSNs) represent a promising solution in the fields of the Internet of Things (IoT) and machine-to-machine networks for smart home applications. However, to feasibly deploy wireless sensor devices in a smart home environment, four key requirements must be satisfied: stability, compatibility, reliability routing, and performance and power balance. In this study, we focus on the unreliability problem of the IEEE 802.15.4 WSN medium access control (MAC), which is caused by the contention-based MAC protocol used for channel access. This problem results in a low packet delivery ratio, particularly in a smart home network with only a few sensor nodes. In this paper, we first propose a lightweight WSN protocol for a smart home or an intelligent building, thus replacing the IEEE 802.15.4 protocol, which is highly complex and has a low packet delivery ratio. Subsequently, we describe the development of a discrete event system model for the WSN by using a GRAFCET and propose a development platform based on a reconfigurable FPGA for reducing fabrication cost and time. Finally, a prototype WSN controller ASIC chip without an extra CPU and with our proposed lightweight MAC was developed and tested. It enhanced the packet delivery ratio by up to 100%.

Reversible contrast mapping (RCM) and its various modified forms are used extensively in reversible watermarking (RW) on digital images to embed secret information. Sometimes RW demands real-time implementation that can be made by hardware realization and RCM-based RW becomes appealing due to its integer transform nature followed by least significant bit (LSB) substitution for embedding. This motivates us to propose RCM-RW on digital images with two objectives: modification on the existing RCM algorithm to increase embedding rate with low visual distortion. Later on, prototype design through field-programmable gate array (FPGA) is developed for a (256 × 256), 8-bit gray scale image using (32 × 32) image block and pipeline architecture. For a cover image of size (256 × 256), the proposed architecture requires 8,971 slices, 8,246 slice flip-flops, 9,706 numbers of four-input LUTs and 2 FIFO 16/RAMB for watermark embedding purpose. Proposed architecture consumes a power of 636mW and offers a data rate of 1.0493Mbps at an operating frequency as high as 95.3MHz.

Multiplier-free fast algorithms are derived and analyzed for realizing the 8-point discrete sine transform of type II and type VII (DST-II and DST-VII) transforms with applications in image and video compression. A new fast algorithm is identified using numerical search methods for approximating DST-VII without employing multipliers. In addition, recently proposed fast algorithms for approximating the 8-point DCT-II are now extended to approximate DST-II. All proposed approximations for DST-II and DST-VII are compared with ideal transforms, and circuit complexity is measured using FPGA-based rapid prototypes on a 90nm Xilinx Virtex-4 device. The proposed architectures find applications in emerging video processing standards such as H.265/HEVC.

This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using the proposed comparator requires 206 minimum-sized transistors and provides large area saving compared to previously proposed designs. Thermometer code is partitioned using algebraic division theorem. This conversion is used for mathematical modeling and complexity reduction of decoder circuit using semi-parallel organization of comparators. Circuit is designed using 90 nm technology which exhibits satisfactory performance even in process variation.

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 $\mu$m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 $\mu$s. It only drains 60 $\mu$A from a 3.3 V supply.

In this paper, a $G_m$-$C$ low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22dBm, in-band noise density is 100nV/$\surd$Hz and power consumption is 5.9mW. The supply voltage of the filter is equal to 1V.

The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time.

Presented work deals with applications of the single $z$-copy controlled-gain voltage differencing current conveyor (ZC-CG-VDCC) in single purpose and multifunctional biquadratic voltage- and current-mode active resistor-less filters. Electronically adjustable features of the active device (intrinsic current input resistance $R_x$, current gain $B$ and transconductance $g_m$) are controlled by DC bias current. These mentioned adjustable features allow interesting possibilities of control of the pole frequency and quality factor. Four voltage-mode solutions realizing low-pass, band-pass, high-pass and band-reject filtering solutions were designed together with two current-mode filters. The current-mode solutions have curious multifunctional capability based on full utilization of electronically controllable parameters of the ZC-CG-VDCC. Two adjustable parameters of the ZC-CG-VDCC (intrinsic current input resistance and transconductance) are used for electronic setting of features of the filter (pole frequency, quality factor, tuning). Control of the third adjustable parameter (current gain) causes reconnection-less change of the transfer function between iAP (inverting all-pass response) and iBR (inverting band-reject responses). Simulation results in PSPICE and Cadence CDS 6 are used to show characteristics of the proposed circuits.

This paper presents a quad-mode dual-band bandpass filter (BPF) using one shorted stub and two pairs of open stubs. The proposed filter simultaneously operates at Bluetooth (2.4–2.485GHz) and WLAN (5.1–5.35GHz) band. The filter has been designed and fabricated on Rogers’s RO4350 substrate and has a size of 13 × 12.26mm².