Journal of Circuits, Systems and Computers

A comparative study based on combined special projections and important frequency-weighted model order reduction (MOR) algorithms to compute optimal approximants for full order digital filters is achieved. It is about the gradient flow (GF) without frequency weighted, the frequency-weighted balanced truncation (FWBT), the GF with frequency weighted (FWGF) and the frequency cross-gramian (CGF) techniques, where special projections of frequency-weighted approximation are used. The obtained low order approximants are expected to follow the original digital filter behavior. With the aim of highlighting the best technique from their implementation, a comparative study is achieved when comparing with a robust MOR technique. Furthermore, two robust performance tools are used namely, the $L_2$ norm, and the integral-squared error (ISE) allowed to conclude on the efficiency of the best approximation algorithm.

The development of bidirectional DC–DC converters has become important because of their requirement in energy-storage systems. The simple structure of nonisolated bidirectional DC–DC converter types includes multilevel, switched-capacitor, buck-boost, and coupled inductor type. In multilevel and switched-capacitor types, if large voltage gain must be provided, more switches and capacitors are required. Since the leakage inductor energy cannot be recycled, voltage stresses on the switches are present. Therefore, the control strategy is easily implemented in the system operation. This paper presents a cascaded nonisolated dc–dc switched coupled converter for enhancement of the switching operation. For the optimal switching performances, an Artificial Intelligence (AI) technique is utilized. The AI technique is the Adaptive Neuro-Fuzzy Inference System (ANFIS) for generating the optimal control pulses to enhance the performance of boost and buck switch. In addition, the proposed technique is utilized in cascaded nonisolated DC–DC switched coupled converter to reduce the losses. In the ANFIS technique, the error voltage and change in error voltage are given as inputs. At the same time, the ANFIS controller is employed to reduce the error value and produce the optimized gain pulses. In the buck and boost switch mode of operation, it is enhanced with the help of the proposed technique. Moreover, the operating principle and voltage conversion ratio are discussed. It is seen that the implementation of the proposed controller improves the efficiency of the system and also reduces the voltage drop across the switching operation. Then the proposed ANFIS technique with bidirectional converter topology was implemented in MATLAB/Simulink working platform and the output performance is analyzed. Then the proposed circuit performance is compared to the existing circuit such as proportional integral derivative (PID), artificial neural network (ANN) and Fuzzy, respectively.

Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180nm CMOS standard cell library show that the proposed architectures for the three-moduli set $\{2^{16}-1,2^{16},2^{16}+1\}$ are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.

The safety of cryptosystems, mainly based on algorithmic improvement, is still vulnerable to side-channel attacks (SCA) based on machine learning. Multi-class classification based on neural networks and principal components analysis (PCA) can be powerful tools for pattern recognition and classification of side-channel information. In this paper, an experimental investigation was conducted to explore the efficiency of various architectures of feed-forward back-propagation (FFBP) neural networks and PCA against side-channel attacks. The experiment is performed on the data leakage of an FPGA implementation of elliptic curve cryptography (ECC). Our results show that the proposed method is a promising method for SCA with an overall accuracy of 88% correct classification.

Mean Value Analysis (MVA) has long been a standard approach for performance analysis of computer systems. While the exact load-dependent MVA algorithm is an efficient technique for computer system performance modeling, it fails to address multi-core computer systems with Dynamic Frequency Scaling (DFS). In addition, the load-dependent MVA algorithm suffers from numerical difficulties under heavy load conditions. The goal of our paper is to find an efficient and robust method which is easy to use in practice and is also accurate for performance prediction for multi-core platforms. The proposed method, called Approximate Performance Evaluation for Multi-core computers (APEM), uses a flow-equivalent performance model designed specifically to address multi-core computer systems and identify the influence on the CPU demand of the effect of DFS. We adopt an approximation technique to estimate resource demands to parametrize MVA algorithms. To validate the application of our method, we investigate three case studies with extended TPC-W benchmark kits, showing that our method achieves better accuracy compared with other commonly used MVA algorithms. We compare the three different performance models, and we also extend our approach to multi-class models.

Terahertz band has recently attracted the attention of the communication society due to its huge bandwidth and very high-speed wireless communications capability. It has been utilized in a variety of disciplines including physics, biology and astronomy for years; and the main concerns have always been obtaining highly efficient and high-power terahertz sources. Today, these problems are still the most important issues in establishing an operable wireless terahertz communication link. In this paper, recent studies in the field of terahertz source design are investigated based on the terahertz output power and efficiency. Solid-state sources and optical sources were comparatively reviewed with optical photoconductive material (OPM)-based methods which are combined with the terahertz antennas in the design phase generally. For wireless communication, the most suitable frequencies are between 0.3THz and 1THz due to the attenuation profile of the atmosphere. For this reason, based on the recently published studies, it has been observed that OPM and resonant tunneling diode-based sources are the most promising terahertz sources in terms of efficiency and power. Key issues and the main problems of terahertz photoconductive antennas which are the base of OPM method were also discussed in this paper.

This paper describes improvements in a Farrow-structured variable fractional delay (FD) Lagrange filter for all-pass FD interpolation. The main idea is to integrate the truncated sinc into the Farrow structure of a Lagrange filter, in order that a superior FD approximation in the least-square sense can be achieved. Its primary advantages are the lower level of mean-square-error (MSE) over the whole FD range and the reduced implementation cost. Extra design parameters are introduced for making the trade-off between MSE and maximal flatness under different design requirements. Design examples are included, illustrating an MSE reduction of $50\%$ compared to a classical Farrow-structured Lagrange interpolator while the implementation cost is reduced. This improved variable FD interpolation system is suitable for many applications, such as sample rate conversion, digital beamforming and timing synchronization in wideband software-defined radio (SDR) communications.

This paper deals with the control of the memristor-based simplest chaotic circuit by means of only one-state controller. Three distinct control techniques, namely linear feedback control, sliding mode control, and nonlinear control, are examined for the control. Routh–Hurwitz stability criteria are used for constructing the linear feedback and sliding mode gains. Lyapunov function is used for ensuring the global asymptotic stability of the system with the nonlinear controller. Numerical simulations are demonstrated not only to validate the theoretical analyses, but also to compare the control results. They have shown that even if one-state controller is used, all the methods are effective for controlling the memristor-based simplest chaotic circuit. However, the control is observed in a better time period with the sliding mode controller.

A new impulse radio-ultra wideband (IR-UWB) communication system with quadrature phase shift keying (QPSK) modulation scheme was presented in this research. The system utilized orthogonal property of fourth- and fifth-order derivatives of Gaussian pulses for modulation and time hopping (TH) multiple-access scheme. This system was compared with conventional TH-PPM and TH-BPSK systems at the same condition. The simulation results in multipath channel showed that the proposed system can provide better bit rate performance compared with the conventional IR-UWB system. A very low power and low complexity circuit for generation of the fourth-order derivative of Gaussian pulse was also proposed. The circuits of fourth- and fifth-order derivatives of Gaussian pulses were simulated using a 0.18$\mu$m CMOS technology. The core chip size was only 0.015mm². The output amplitude pulse yielded 135mV peak to peak under a supply voltage of 1.8V. The energy consumption of the fourth- and fifth-order derivatives of Gaussian pulses circuits were 8pJ/pulse for 200MHz pulse-repeating frequency (PRF).

This paper deals with the smart applications of multirate digital signal processing. The two major operations are accomplished in consumer electronics and communication engineering. The process of reducing the sampling frequency of a sampled signal is called decimation. In the usage of decimating filters, only a portion of the out-of-pass band frequencies aliases into the pass band, in systems wherein different parts operate at different sample rates. A filter design, tuned to the aliasing frequencies all of which can otherwise stealth into the pass band, not only provides multiple stop bands but also exhibits computational efficiency and performance superiority over the single stop band design. The proposed method of transmultiplexer using decimation and interpolation filters analysis procedure is not only efficient but also opens up a new vista of being simple and elegant to compute for the desired over and above transmultiplexer.

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405MHz medical implant communications service (MICS) band applications using 0.18-$\mu$m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5dB conversion gain, 1.85dB noise figure, and IIP3 of $-30$dBm while consuming 440$\mu$W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29mm².

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to raise the level of abstraction for the design and optimization. A better optimization of performance and power can be achieved at higher abstraction levels by applying suitable optimization techniques. Insertion of clock gating logic into the generated Register-Transfer Level (RTL) would facilitate lowering dynamic power consumption by switching off the clock signal to portions of the circuit not currently in use and thereby reducing unnecessary toggling. In this work, we have tried to minimize the power consumption of synchronous circuits by reducing the number of activity string patterns. Activity-driven clock trees have been used wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies additional control signals and gates, there is always a trade-off existing between the logic circuit area overhead and the total power consumption of the clock tree. A pseudo-Boolean satisfiability (PB-SAT)-based approach is proposed in this work which focuses on the reduction of power consumption by reducing the activity pattern of the clock tree which will reduce the power consumption with appropriate module-binding solutions.

In this paper, a developed structure for DC–DC quasi-Z-source (QZS) converters is proposed. First, the proposed two-stage structure is presented and analyzed. Then, the proposed structure is extended to $n$ stages and its relations are calculated. Compared with other conventional structures, the proposed structure has higher voltage gain and higher reliability. The proposed topology is suitable for high power applications. To have the correct performance of conventional QZS converter, all impedance network elements must be intact. In the case of small failure in one of the elements, the operation of the whole system is disrupted. The proposed structure has high reliability because when one stage fails, the fault management system separates that stage from the other stages and the remaining stages continue to transmit power. In this paper, in addition to analyzing the operation of the proposed converter in different operating modes, calculations of voltage gain, voltage stresses across capacitors and reliability analysis are also presented. Reliability is calculated according to well-known Markov model. Moreover, a comprehensive comparison in terms of voltage gain and reliability is made between the proposed converter and the other conventional structures. Also, the rating values of inductors and capacitors are designed. Finally, experimental and simulation results are presented by using power system computer-aided design (PSCAD) software to verify the theories.

This paper proposes a simple and passive harmonic reduction method at dc link of 20-pulse rectifier. The 20-pulse topology is obtained via two paralleled 10-pulse ac–dc converters, each of them consisting of a five-phase (five-leg) diode bridge rectifier. For independent operation of the paralleled diode-bridge rectifiers, a zero sequence blocking transformer (ZSBT) is designed and implemented. Connection of a tapped inter-phase transformer (IPT) at the output of the ZSBT results in doubling the number of the output voltage pulses. The application of the pulse doubling technique with a low power rating (2% of the load power rating) results in a simpler and more economical configuration of the whole system and increased number of pulses. The design is suitable for retrofit applications where a six-pulse diode bridge rectifier is being utilized. The proposed structure is simulated using Matlab/Simulink software under different loading conditions. The simulation results confirm the significant improvement of the power quality indices (IEEE-519 standard requirements) at the point of common coupling (PCC). Experimental results are obtained using the designed and constructed laboratory prototype of the proposed converter to validate the design procedure and the simulation results. The VA rating of the magnetic circuit is calculated to confirm the savings in space, volume, weight and cost of the proposed configuration.

In this paper, a novel high step-up single switch DC–DC converter with soft switching is presented. The main application of this converter is the connection of photovoltaic (PV) system to a 400V DC-bus. The proposed converter achieves high step-up voltage gain with small duty cycle by a combined boost and fly-back topology. Also, its switch voltage stress is lower than the output voltage. Besides, in the proposed converter, any auxiliary switch or magnetic core has not been used — therefore, the number of converter components has not been increased much in comparison with the conventional boost-fly-back converter. The operation principles of the converter and its theoretical operation waveforms are presented. In order to evaluate the theoretical analysis, a prototype of the converter is designed and experimentally implemented. The practical results are presented for a 100W boost-fly-back converter with input voltage of 40V and output voltage of 400V. Also, the output capacitor is designed to have less than 1% ripple on output voltage.

The need for efficient Finite Impulse Response (FIR) filters in high-speed applications such as telecommunications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offers many advantages, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. Experimental results show a throughput of 7.2GSPS with an operating frequency of only 450MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.44 times faster than the state-of-the-art solution for a filter length of 16 and a promising 1.04GSPS throughput is achieved for a higher order of length 61. Incorporated into a generic Quadrature Amplitude Modulation (QAM) transmitter fitted with Forward Error Correction technique, a maximum throughput of 23Gb/s is achieved by the system for processing 16 input samples in parallel. In comparison to the state-of-the-art mixed domain approach, a threefold performance gain, while utilizing comparatively less Look-up Tables (LUTs), registers and DSP48 slices with an average gain factor of 43.3$x$, 4.7$x$ and 3.9$x$, respectively, is accomplished.

Femtocell plays a significant role in technologies to improve service quality and data rates for indoor mobile users. It is the recent less expensive concept that provides better indoor coverage. Therefore, handoff process from macrocell to femtocell is an open research issue. In this paper, an adaptive macro/femto handoff scheme is proposed. It takes into consideration the velocity of mobile station, load balancing and the accessing mode of the target cell. It effectively handles the indoor handoff situations by checking user velocity which has to be lower than a threshold value in order to guarantee that this user has a sufficient time to switch from macrocell to femtocell. The proposed scheme aims to achieve load balancing between macrocells and femtocells. It also minimizes the number of femtocells in the neighbor cell list. The target femtocell is predicted based on the direction of the mobile user considering the femtocells accessing mode. Numerical results show that the proposed scheme improves femtocell usage and decreases the handoff latency and the total handoff delay compared to the standard macrocell-to-femtocell handoff process and other existing schemes.

The electrocardiogram (ECG) signal is widely used for diagnosis of heart disorders. However, ECG signal is a kind of weak signal to be interfered with heavy background interferences. Moreover, there are some overlaps between the interference frequency sub-bands and the ECG frequency sub-bands, so it is difficult to inhibit noise in the ECG signal. In this paper, the ECG signal in-band noise de-noising method based on empirical mode decomposition (EMD) is proposed. This method uses random permutation to process intrinsic mode functions (IMFs). It abstracts QRS complexes to separate them from noise so that the clean ECG signal is obtained. The method is validated through simulations on the MIT-BIH Arrhythmia Database and experiments on the measured test data. The results indicate that the proposed method can restrain noise, improve signal noise ratio (SNR) and reduce mean squared error (MSE) effectively.

An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture, while supporting dynamic adaptation to voltage noises. The proposed ADMFC uses dedicated high-speed carry chain paths in an FPGA to finely adjust the clock frequency by controlling the number of carry propagations on the carry chain logics (CARRY4 cells) in the delay line of a ring oscillator. Moreover, supply voltage variation and noise caused by circuit switchings can be compensated by dynamically adjusting the length of ripple carry propagations on the cascaded CARRY4 cells in response to the detected voltage variation. Finally, a selectable modulation profile is devised to provide a much suitable profile between two different profiles at run-time for the given noise constraints and working environment of a chip. Measurement results show that at the frequency of 44.6MHz, the ADMFC can obtain 17dB and 19.4dB EMI attenuations with a 7.5% spreading ratio when using triangular and sawtooth profiles, respectively. The proposed ADMFC is suitable for applications such as biological sensor nodes or IoT related systems which typically operate at a low-frequency band.