Journal of Circuits, Systems and Computers

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

Micro-Electro-Mechanical System (MEMS) capacitive accelerometers have received extensive attention in recent years due to their excellent performance indicators; especially in the fields of noise, power consumption, and bias instability, great development and progress have been made. In the field of noise, effective noise reduction is achieved by introducing oversampling modulation technology combined with digital noise reduction technology. In power consumption, the power consumption of the accelerometer is effectively reduced by using the successive approximation structure in the interface circuit and using the finite state machine for precise control. In bias instability, the effects of temperature offset and zero-point drift are suppressed by using a hybrid topology connection structure in the interface circuit, and an effective reduction of bias instability is achieved. In this paper, the research and progress of MEMS capacitive accelerometer in the field of noise, power consumption and bias instability are reviewed, and the articles published in recent years are listed and summarized and prospected.

In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed interface trap charges (ITCs) at the Si–SiO₂ interface. During the analysis, both types of trap charges, positive (donor) and negative (acceptor), have been considered to investigate their effect on the DC, analog/ radio frequency, linearity and harmonic distortion performance parameters in terms of the carrier concentration, electric field, band-to-band tunneling rate, transfer characteristics, transconductance ($g_m$), unity gain frequency ($f_T$), gain–bandwidth product, device efficiency ($g_m$/$I_{\mathrm{\text{DS}}}$), transconductance frequency product, transit time ($\tau$), second- and third-order transconductance and voltage intercept points ($g_{m2}$, $g_{m3}$, VIP2 and VIP3), third-order Input Intercept Point and Intermodulation Distortion (IIP3, IMD3), second-, third-order and total harmonic distortions (HD2, HD3 and THD), respectively. Further, the impact of temperature variations from $200$K to $500$K in the presence of ITCs is investigated and the results are compared with conventional DMSGO-TFET. In terms of percentage variation, DMSGO-SDP-TFET depicts lower variation than conventional DMSGO-TFET, indicating that the proposed device is more immune to trap charges and can be used for energy-efficient, high-frequency and linearity applications at elevated temperatures.

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm.

In deep learning, convolutional neural networks (CNNs) are a class of artificial neural networks (ANNs), most commonly applied to analyze visual imagery. They are also known as Shift-Invariant or Space-Invariant Artificial Neural Networks (SIANNs), based on the shared-weight architecture of the convolution kernels or filters that slide along input features and provide translation-equivariant responses known as feature maps. Recently, various architectures for CNN based on FPGA platform have been proposed because it has the advantages of high performance and fast development cycle. However, some key issues including how to optimize the performance of CNN layers with different structures, high-performance heterogeneous accelerator design, and how to reduce the neural network framework integration overhead need to be improved. To overcome and improve these problems, we propose dynamic cycle pipeline tiling, data layout optimization, and a pipelined software and hardware (SW–HW)-integrated architecture with flexibility and integration. Some benchmarks have been tested and implemented on the FPGA board for the proposed architecture. The proposed dynamic tiling and data layout transformation improved by 2.3 times in the performance. Moreover, with two-level pipelining, we achieve up to five times speedup and the proposed system is 3.8 times more energy-efficient than the GPU.

In public-key cryptography, the RSA algorithm is an inevitable part of hardware security because of the ease of implementation and security. RSA Cryptographic algorithm uses many modular arithmetic operations that decide the overall performance of the architecture. This paper proposes VLSI architecture to implement an RSA public-key cryptosystem driven by the Residue Number System (RNS). Modular exponentiation in the RSA algorithm is executed by dividing the entire process into modular squaring and multiplication operations. Based on the RNS employment in modulo-exponential operation, two RSA architectures are proposed. A Verilog HDL code is used to model the entire RSA architecture and ported in Zynq FPGA (XC7Z020CLG484-1) for Proof of Concept (PoC). The Cadence Genus Synthesizer tool characterizes a system’s performance for TSMCs standard Cell library. Partial RNS (Proposed-I)- and Fully RNS (Proposed-II)-based RSA architectures increase the operation speed by 13% and 35%, respectively, compared with the existing RSA. Even though there is an increase in parameters like area, power and PDP for a smaller key size, the improvement in area utilization and encryption/ decryption speed of RSA for a larger key size is evident from the analysis.

It is crucial to correctly assess whether a potential borrower can repay the loan in the credit scoring model. The credit loan data has a serious data imbalance because the number of defaulters is far less than the nondefaulters. However, most current methods for dealing with data imbalance are designed to improve the classification performance of minority data, which will reduce the performance of majority data. For a financial institution, the economic loss caused by the decrease in the classification performance of nondefaulters (majority data) cannot be ignored. This paper proposes an ensemble learning method based on one-class and binary classification (EMOBC) for credit scoring. The purpose is to improve the classification accuracy of the minority class while mitigating the loss of classification accuracy of the majority class as much as possible. EMOBC uses undersampling for the majority class (nondefault samples in credit scoring) and perform binary-class learning on the balanced data to improve the classification accuracy of the minority. To alleviate the decline in classification performance of the majority class, EMOBC uses one-class and binary collaborative classification to train classifiers. The classification result is determined by the average of one-class and binary-class classifiers. The experimental results show that EMOBC has good comprehensive performance compared with the existing methods.

This work describes a new design approach for a four-stage ring Voltage-Controlled Oscillator (VCO) for Orthogonal Frequency Division Multiplexing (OFDM) systems, which is ideal for low-phase noise and low-power applications. The phase noise of the proposed ring VCO has been improved by limiting the delay cell’s output current to a relatively narrow portion of the output waveform, and the complementary nature of the delay cell prevents the power from increasing substantially. The proposed VCO is designed and simulated in GPDK 90nm CMOS technology using Cadence Virtuoso under 1.0V power supply. A tuning frequency range of 112–362MHz is obtained with control voltage ranges 0.0–1.0V. The proposed ring VCO consumes 1.07mW of power. At a 1MHz offset frequency, phase noise reduction is achieved to $-109.36$dBc/Hz. The proposed design is also validated by the Process–Voltage–Temperature (PVT) analysis. The proposed VCO has a Figure of Merit (FOM) of $-160.24$dBc/Hz and acquires a total area of 0.00085mm².

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the existing CMOS technology. The device has involved in various applications from memory design to analog and digital circuit design. In this paper, a combination of memristor devices and CMOS transistors is working together to form a hybrid CMOS-memristor circuit for XAX- Module, a core element used as digital circuit for elliptic curve cryptography. The proposed design was implemented using Pt/TaOx/Ta memristor device and simulated in Cadence Virtuoso. The simulation results demonstrate the design functionality. The proposed module appears to be efficient in terms of layout area, delay and power consumption since the design utilizes the hybrid CMOS/memristor gates.

In the Internet of Things (IoT) era, an immense amount of sensing devices are obtained and produce various sensory data over time for a wide range of disciplines and applications. These devices will result in significant, fast, and real-time data streams based on the utilization characteristics. Utilizing analytics over such data streams to identify new information, model future insights, and make control decisions is a necessary process that makes IoT a worthy paradigm for businesses and a quality-of-life improving technology. This paper presents a study of digital agriculture and its significance in terms of the application of an IoT-based device — a two-wheeled self-balancing robot — followed by a thorough procedural explanation of the development of the device, which begins with the mathematical modeling of the system through the Euler–Lagrange method to obtain the equations of motion for the same and linearize the equation to define the control method to be used to balance the robot structure, all based on the concept of the inverted pendulum. Then paper discusses the suitable and the most efficient control method, which is the linear quadratic regulator (LQR), for these robots. Then deep learning-based LQR (DL-LQR) method is implemented in the robots performing the algorithm to balance it successfully.

With the prevalence of artificial intelligence technologies, big data has been utilized to higher extent in many cross-domain fields. This paper concentrates on the digital assessment of vocational education level in some specific areas, and proposes a graph neural network-based assessment model for this purpose. Assume that all vocational colleges inside a specific region are with a social graph, in which each college is a node and the relations among them are the edges. The graph neural network (GNN) model is formulated to capture global structured features of all the nodes together. The GNN is then employed for the sequential modeling pattern, and the evolving characteristics of all the colleges can be captured. Some experiments are also conducted to evaluate the performance of the proposed GNN-VEL. It is compared with two typical forecasting methods under evaluation of two metrics. The results show that it performs better than other two methods.

At present, there are many semantic segmentation algorithms with excellent performance for intelligent driving vehicles, but most of them only work well on scenes with good illumination. In order to solve the problem of scene segmentation under low illumination, this paper proposes a novel semantic segmentation algorithm that combines visible and infrared images. In this algorithm, two parallel encoders are designed as the input of the images, and the decoder divides the fused images output from the encoder. The model is based on ResNet algorithm, and the residual attention module is used in each branch to mine and enhance the spatial features of multilevel channels to extract images information. Experiments are carried out on publicly available thermal infrared and visible datasets. The results show that the algorithm proposed in this paper is superior to the algorithm using only visible images in semantic segmentation of traffic environment.

The real-time monitoring and detection of the fruit carrying for monorail transporter in the mountain orchard are significant for the transporter scheduling and safety. In this paper, we present a fruit carrying monitoring system, including the pan-tilt camera platform, AI edge computing platform, improved detection algorithm and the web client. The system used a pan-tilt camera to capture images of the truck body of the monorail transporter, realizing monitoring of fruit carrying. Besides, we present an improved fruit carrying detection algorithm based on YOLOv5s, taking the “basket”, “orange” and “fullbasket” as the object. We introduced the improved attention mechanism E-CBAM (Efficient-Convolutional Block Attention Module) based on CBAM, into the C3 module in the neck network of YOLOv5s. Focal loss was introduced to improve the classification and confidence loss to improve detection accuracy; to deploy the model on the embedded platform better, we compressed the model through the EagleEye pruning algorithm to reduce the parameters and improve the detection speed. The experiment was performed on the custom fruit-carrying datasets, the mAP was 91.5%, which was 9.6%, 9.9% and 12.0% higher than that of Faster-RCNN, RetinaNet-Res50 and YOLOv3-tiny, respectively, and detection speed at Jetson Nano was 72ms/img. The monitoring system and detection algorithm proposed in the paper can provide technical support for the safe transportation of monorail transporter and scheduling transportation equipment more efficiently.

A deep learning-based method, improved YOLOv3 algorithm is proposed in the deep learning environment to tackle challenges such as big scale, uneven distribution, largescale variation, and complicated background of small- and medium-sized remote sensing photos. This manufacture uses Densenet as the backbone, replacing Darknet-53 to realize feature reuse and make the feature extraction more effective; introduces the spatial pyramid pooling module into the feature pyramid part for increasing the receptive field and isolating the most prominent contextual features; adds SE attention module in the process of feature extraction and obtains richer features by learning more location information and channel information from the images. Under DOTA dataset, the final results are that the mean Average Precision value is 86.78%, which is 4.16% higher than the baseline YOLOv3 network. The model put forward makes it easier to extract information from the feature map and achieve higher detection accuracy without influencing the real-time performance of detection.

Currently, the prevalence of various Internet intrusion technologies has brought much challenge to the enterprise management. For many core documents, the information leakage may lead to the loss of secrets of enterprises. Therefore, some core official documents in enterprises are in the format of papers, rather than electronic format. As a consequence, it is of significance to develop automatic information processing techniques for official documents in the format of papers, so as to improve the working efficiency of enterprises. In this paper, a novel business scheduling approach for enterprises via vision sensing-based automatic documental information extraction is proposed. For the first stage, the vision sensing-based optical character recognition (OCR) technique is utilized to extract textual information from official documents in the format of papers. For the second stage, the deep neural network is utilized to output business scheduling results on the basis of digital recognition contents from the first stage. Finally, the experimental simulation is also carried out to verify efficiency of the proposal.

Aiming at the low accuracy of the track signal intrusion detection (IDe) algorithm in the traditional cloud-side collaborative computing environment, this paper proposes a deep learning (D-L)-based track signal IDe method in the cloud edge collaborative computing environment. First, the main framework of the IDe method is constructed by comprehensively considering the backbone network, network transmission and ground equipment, and edge computing (EC) is introduced to cloud services. Then, the The CNN (Convolutional Neural Networks)-attention-based BiLSTM (Bi-directional Long Short-Term Memory) neural network is used in the cloud center layer of the system to train the historical data, a D-L method is proposed. Finally, a pooling layer and a dropout layer are introduced into the model to effectively prevent the overfitting of the model and achieve accurate detection of track signal intrusion. The purpose of introducing the pooling layer is to accelerate the model convergence, remove the redundancy and reduce the feature dimension, and the purpose of introducing the dropout layer is to prevent the overfitting of the model. Through simulation experiments, the proposed IDe method and the other three methods are compared and analyzed under the same conditions. The results show that the F1 value of the method proposed in this paper is optimal under four different types of sample data. The F1 value is the lowest of 0.948 and the highest of 0.963. The performance of the algorithm is better than the other three comparison algorithms. The method proposed in this paper is important for solving the IDe signal in the cloud-edge cooperative environment, and also provides a theoretical basis for tracking the signal IDe direction.

This paper presents an in-depth research analysis on the evaluation of the development quality of regional economy through an improved convolutional neural network algorithm, and uses it to design a fuzzy comprehensive evaluation model for the practical process. Based on the measured indices of different variables, a spatial econometric model is constructed and provincial panel data are selected to empirically analyze the impact and spatial spillover effects of financial agglomeration and technological innovation on regional economic quality development from both static and dynamic aspects and to examine the spatial correlation of the factors. A new serial data flow model is adopted, which optimizes the control of data flow in convolutional computation, reduces the percentage of clock cycles used to read memory data, and increases the computational efficiency. At the same time, with dynamic data caching, a convolutional computation can be completed in one clock cycle, reducing the memory capacity required for caching intermediate data. The effectiveness of the evaluation system constructed in this paper is further tested. Most of the indicators have a significant positive or negative impact on the quality level of economic development, and the direction of the impact is consistent with the positive and negative attributes of the indicators in this study, which verifies the validity of the evaluation indicator system constructed in this paper. In summary of the study, effective suggestions are made in terms of human capital investment, reasonable allocation of fiscal expenditure, enhancing regional greening development and improving risk prevention measures.