3D integration is an emerging technology for the design of many-core microprocessors and memory integration. This book, Advances in 3D Integrated Circuits and Systems, is written to help readers understand 3D integrated circuits in three stages: device basics, system level management, and real designs.
Contents presented in this book include fabrication techniques for 3D TSV and 2.5D TSI; device modeling; physical designs; thermal, power and I/O management; and 3D designs of sensors, I/Os, multi-core processors, and memory.
Advanced undergraduates, graduate students, researchers and engineers may find this text useful for understanding the many challenges faced in the development and building of 3D integrated circuits and systems.
Sample Chapter(s)
Chapter 1: Introduction (858 KB)
Contents:
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- Device Modeling:
- Physical Design:
- Macromodel
- TSV Allocation
- Testing
- Thermal Management:
- Power and Thermal System Model
- Microfluidic Based Cooling
- I/O Management:
- Power I/O Management
- Signal I/O Management
- Sensor
- I/O
- Microprocessor
- Non-volatile Memory
Readership: Advanced undergraduates, graduate students, researchers and professionals dealing with 3D Integrated Circuits and Systems.
Hao Yu is Assistant Professor at the School of Electrical and Electronic Engineering, at Nanyang Technological University (NTU), Singapore, since October 2009, and is also area director of the VIRTUS/VALENS Centre of Excellence at NTU. He obtained his BSc from Fudan University, Shanghai, China, in 1999; and obtained both MSc and PhD degrees from the Electrical Engineering department at UCLA, USA, in 2007, majoring in integrated circuits and embedded computing. He was a senior research staff at Berkeley Design Automation (BDA), one of top-100 start-ups selected by Red-herrings at Silicon Valley, since 2006.
Dr Yu has 150 peer-reviewed and referred publications [conference (104) and journal (46)], 4 books, 5 book chapters, 1 best paper award in ACM Transactions on Design Automation of Electronic Systems (TODAES), 3 best paper award nominations (DAC'06, ICCAD'06, ASP-DAC'12), 3 student paper competition finalists (SiRF'13, RFIC'13, IMS'15), 1 keynote paper, 1 inventor award from semiconductor research cooperation (SRC), and 7 patent applications pending. He is the associate editor of the Journal of Low Power Electronics, and reviewer of multiple journals, and has also served as technical program committee member for several conferences (DAC, ICCAD, ISLPED, and ASSCC). His main research interests are the emerging technology and architecture for big-data computing and communication, such as 3D-IC, THz communication, and non-volatile memory. His industry work at BDA is also recognized with an EDN magazine innovation award and multi-million venture capital funding. He is a senior member of IEEE and member of ACM.
Chuan-Seng Tan is Associate Professor, and Assistant Chair (Graduate Studies) at the School of Electrical and Electronic Engineering, at Nanyang Technological University (NTU), Singapore. He received his BEng. degree in electrical engineering from the University of Malaya, Malaysia, in 1999. Subsequently, he completed his MEng. degree in advanced materials at the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at MIT, USA, and was awarded a PhD degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship from 2003–2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow, and from July 2008–February 2014, he was a holder of the inaugural Nanyang Assistant Professorship. In February 2014, he was promoted to the rank of Associate Professor (with tenure).
His research interests are semiconductor process technology and device physics. He is currently working on process technology of three-dimensional integrated circuits (3-D ICs). He has numerous publications on 3-D technology, including an edited book on Wafer Level 3-D ICs Process Technology (Springer, 2008), and 3D Integration of VLSI Systems (Pan Stanford Publishing, 2011). He provides his service as committee member for the International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, ECS-Wafer Bonding, and ISTDM. He is an associate editor of the Elsevier Microelectronics Journal (MEJ).
