Journal of Circuits, Systems and Computers

Formulae on first and second derivatives of various functions associated with a linear nullator–norator–resistance network such as total input power, driving-point and transfer resistances with respect to parameters are established. As a consequence, the concavity of the driving-point resistance with respect to the system of parameters is obtained which generalizes a scalar result of Schneider. An example is given showing that the driving-point resistance R of a nonreciprocal one-port is not monotone or convex or concave with respect to the system of resistances which shows that the Cohn–Vratsanos and the Shannon–Hagelbarger theorems which characterize R of reciprocal one-port cannot be extended in this way. Next, a simplified variant of the Shannon–Hagelbarger theorem is used to derive separate necessary and sufficient conditions characterizing always well-posed, sometimes ill-posed and always ill-posed classes of linear resistive circuit structures introduced and characterized by Hasler, both new in formulation and proof. This reveals that the form of the second partial derivative of the resistance function is responsible for various kinds of the structural solvability of linear circuits. Alternative "if and only if" criteria for these classes are established. They involve replacements of reciprocal circuit elements by combinations of contractions and removals leading to pairs of complementary directed nullator and directed norator trees with appropriately defined signs, and resemble therefore earlier famous Willson–Nielsen feedback structure and Chua–Nishi cactus graph criteria for circuits containing traditional controlled sources. Finally, the qualitative parts of the Cohn–Vratsanos and the Shannon–Hagelbarger theorems are shown to be simple consequences of much more general principles governing all aspects of life, such as maximal entropy and energy conservation laws.

This paper presents the design of tunable heterodyne filter that can be used very effectively in the elimination of narrowband interference in wide-band communications. The filter makes use of the heterodyne process to create a tunable notch filter from a fixed coefficient high-pass filter. It has been shown that it is possible to generate a signal that can be used to set the heterodyne frequency to match the tunable heterodyne notch filter to the center of the detected interference through the use of a simple second order IIR band-pass filter to detect the narrowband interference. Moreover various options have been illustrated for the implementation of heterodyne filters using Xilinx Virtex field programable gate arrays (FPGAs).

In this paper we present a delay analysis of an ATM multiplexer handling multimedia traffic of two classes: real time class, e.g., live audio and video and nonreal time class, e.g., file transfers. Packets arrive into the multiplexer in batches of general size and are output one at a time. The arrivals are homogeneous in the sense that either the arriving batch is all class-1 packets or all class-2 packets. The multiplexer is modeled as a priority discrete time queueing system with batch arrivals and geometric service. The homogeneity of the arrivals is reflected by the addition of an indicator random variable into the model. The analysis is comprehensive in that it covers the three main delay measures: the unfinished work, the busy period and the waiting time. For these measures, probability generating functions are derived, from which moments of arbitrary orders can be obtained. However, only the first moments are obtained in the article to produce expected values. Presented at the end is a special case when the arriving batches are of Poissonian size. Some numerical values are obtained and plotted for this case.

A VLSI chip is fabricated by integrating several rectangular circuit blocks on a 2D silicon floor. The circuit blocks are assumed to be placed isothetically and the netlist attached to each block is given. For wire routing, the terminals belonging to the same net are to be electrically interconnected using conducting paths. A staircase channel is an empty polygonal region on the silicon floor bounded by two monotonically increasing (or decreasing) staircase paths from one corner of the floor to its diagonally opposite corner. The staircase paths are defined by the boundaries of the blocks. In this paper, the problem of determining a monotone staircase channel on the floorplan is considered such that the number of distinct nets whose terminals lie on both sides of the channel, is minimized. Two polynomial-time algorithms are presented based on the network flow paradigm. First, the simple two-terminal net model is considered, i.e., each net is assumed to connect exactly two blocks, for which an O(n×k) time algorithm is proposed, where n and k are respectively the number of blocks and nets on the floor. Next, the algorithm is extended to the more realistic case of multi-terminal net problem. The time complexity of the latter algorithm is O((n+k)×T), where T is the total number of terminals attached to all nets in the floorplan. Solutions to these problems are useful in modeling the repeater block placement that arises in interconnect-driven floorplanning for deep-submicron VLSI physical design. It is also an important problem in context to the classical global routing, where channels are used as routing space on silicon.

In massively parallel systems, the performance gains are often significantly diminished by the inherent communication overhead. This overhead is caused by the required message passing resulting from the task allocation scheme. In this paper, techniques to reduce this communication overhead by both scheduling the communication and determining the routing that the messages should take within a tightly-coupled processor network are presented. Using the recently developed Collision Graph model, static scheduling algorithms are derived which work at compile-time to determine the ordering and routing of the individual message transmissions. Since a priori knowledge about the network traffic required by static scheduling may not be available or accurate, this work also considers dynamic scheduling. A novel hybrid technique is presented which operates in a dynamic environment yet uses known information obtained by analyzing the communication patterns. Experiments performed show significant improvement over baseline techniques.

The power quality has become a major concern since late 1980's. There has been increasing interest in studying power quality problems, one of which is the existence of the current/voltage harmonics. In order to eliminate these harmonics, different methods have so far been proposed and developed. In this paper, line current harmonics reduction is achieved by using an active filter. More specifically, our aim is to introduce a proper control design method for the current control part of the active filter. To achieve the goal, two different predictive controllers are examined. Due to the existing physical constraints (switching frequency and computational limits) in real applications, a new predictive control approach is proposed. The performance of this controller is compared to those obtained by two existing predictive controllers as well as commonly used PI controller through computer simulations considering various circumstances.

In this paper, the one-dimensional Gray–Markel lattice-ladder discrete filter structure is extended to two dimensions (2D). The proposed 2D circuit implementation has minimal number of unit delays. Based on this circuit implementation the corresponding 2D state space realization is derived. The matrices A, b, c′ and the scalar d of the 2D state space model are presented in generalized closed form, having minimal dimension.

The properties of a 2D discrete transfer function with degree of each variable being unity are discussed. The coefficients of the denominator polynomial contain a parameter k (having real values) whose bounds are determined by stability considerations. These bounds are obtained by testing the overall polynomial at only four points z₁=±1 and z₂=±1. Suitable numerator polynomial can be associated to get the overall transfer function. Such structures can be cascaded so that the overall magnitude response can be changed by altering the response of one or more sections.

This paper gives a simple proof for the positiveness of two important symmetric Toeplitz matrices used in communication and signal processing. It utilizes the shifting property of a so-called Uniformly Band-Restricted (UBR) function, which is the generating function for a generic functional symmetric matrix. It is shown that the functional symmetric matrix is positive definite if the UBR function is evaluated at a sequence of distinct real numbers.

Multiway Decision Graphs (MDGs) have recently been proposed as an efficient representation for RTL designs. In this paper, we illustrate the MDG-based formal verification technique on the example of the Island Tunnel Controller. We investigate several techniques on how to deal with the nontermination problem of abstract state exploration, including a novel method based on retiming and circuit transformation. We provide comparative experimental results for the verification of a number of properties for the example using two well-known ROBDD-based verification tools, namely, SMV (Symbolic Model Verifier) and VIS (Verification Interacting with Synthesis), and we show the strength of the MDG approach to handling arbitrary data widths.

In this paper, the effect of mixture tying on a second-order 2D Hidden Markov Model (HMM) is studied as applied to the face recognition problem. While tying HMM parameters is a well-known solution in the case of insufficient training data that leads to nonrobust estimation, it is used here to improve the overall performance in the small model case where the resolution in the observation space is the main problem.

The fully-tied-mixture 2D HMM-based face recognition system is applied to the facial database of AT&T and the facial database of Georgia Institute of Technology. The performance of the proposed 2D HMM tied-mixture system is studied and the expected improvement is confirmed.

The development of multiple Discrete Multitone (DMT) Digital Subscriber Line (DSL) flavors on a single platform can benefit considerably by a programmable architecture, which feature Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), especially when fast prototyping is targeted. However, the flexibility assumed to be offered by algorithmic partitioning does not automatically and proportionally simplify the digital signal processing algorithms, unless the effects of overflow/saturation in intermediate processing stages are carefully studied. The effects of overflow/saturation in intermediate stages is very critical throughout the design process, since the operations involved are nonlinear in nature and affect the most significant bits of the computational process. This paper presents an efficient soft-core implementation of a Block Floating Point FFT (BLFP) algorithm, designed for a Very high-speed DSL (VDSL) DMT systems and for the full variety of other xDSL DMT flavors, as the latter demand an extended dynamic range to achieve performance that may otherwise be only warranted by costly floating-point chip implementations.