Journal of Circuits, Systems and Computers

A high-performance versatile motion estimation processor with regular hardware and control structure capable of MP@HL is presented. It can compute 1920 × 1080 pels in 4096 cycles within search point range 64 with eight identical processors. The presented processor has 100% hardware utilization by eliminating the computation delay between stages, and the capability to compute half pel precision motion estimation. Also, by enhancing image data reuse, the I/O bottleneck problem is alleviated. With efficient scalability, the amount of hardware and computation speed can be easily adjusted for a variety of application areas. The proposed edge effect hardware can be used for object-based coding for MPEG-4. The processor was verified with C++ and VHDL based on actual image data and implemented with 0.6μm gate array. Also, a motion estimator system with image memories and PC host interface was designed.

The low resolution of ultrasonic images is mainly caused by the convolution between the reflect function of the measured tissues and the system impulse response. In this paper, the system impulse response is first estimated on the envelope ultrasonic image data using higher-order spectra. Subsequently, wavelet-based deconvolution is implemented. The algorithm proposed in this paper removes the coupling problem between the tissue signals and the impulse response, which has been a puzzle in homomorphic deconvolution. It also preserves spatial components of ultrasonic images much better compared to Fourier domain deconvolution. The resulting images behave clearer in velamen boundary and tissue layers, and the texture information also appears more detailed. The deconvolved images achieve good resolution gains in both axial and lateral directions.

Substrate coupling is a phenomenon that affects the behavior and performance of RF and mixed signal ICs. Prediction of such crosstalk during the design process can help designers. In this paper, a new methodology is presented for performing a fast and reliable characterization of the noise transmission path, modeling the substrate as a resistive network. Adopting only DC measurement techniques, the dependence of disturbances attenuation on the geometric parameters is found. Moreover, the relation between attenuation and disturbance types is indicated. Finally, a qualitative comparison is made between the efficiency of the most commonly used technology measures against substrate crosstalk.

This letter shows how, by simple modifications, the four-current-conveyor (CC) voltage mode biquad filter recently proposed by Singh and Senani provides dual function capability, i.e., the same circuit also yields all the five current-mode (CM) filters.

A new highly reconfigurable Manchester adder for low-power media signal processing is presented. The proposed circuit can be run-time partitioned. Its 64-bit version performs one 64-, two 32-, four 16-, or eight 8-bit additions. When the AMS 0.35 mm 2-poly 3-metal 3.3 V CMOS (CSD) process is used to produce a layout, an energy dissipation of only 78 pJ and a worst propagation delay of about 10.2 ns are obtained. The novelty demonstrated in this letter is that the introduction of dummy bit positions along the carry-path can be avoided using on-purpose dynamic logic stages.

Optimizing area and speed in parallel prefix circuits has been considered important for a long time. The issue of power consumption in these circuits, however, has not been addressed. This paper presents a comparative study of different parallel prefix circuits from the point of view of power–speed trade-off. An effective circuit capacitance model that is verified through PSpice simulations is used to investigate the power consumption in parallel prefix circuits. The model results in an analytical function for power consumption for each prefix circuit considered. The degrees of freedom studied include different parallel prefix circuits and voltage scaling. The results of the study were applied to evaluate power–speed trade-offs when different prefix circuits are used in Brent's parallel adder.⁵

An inductorless realization of nonautonomous (Murali–Lakshmanan–Chua) MLC chaotic circuit is proposed. The main purpose of this study is to improve the performance of nonautonomous MLC chaotic circuit using only CFOAs. CFOA-based topology used in this realization enables to simulate floating inductance. This modification provides to the designer wideband chaotic signals for secure communication systems. In addition to this major improvement, a CFOA-based nonlinear resistor was used in the new realization of nonautonomous MLC chaotic circuit. The usage of CFOA-based inductance simulator and nonlinear resistor in the circuit structure reduces the component count and provides isolated outputs. The performance of the proposed inductorless nonautonomous chaotic circuit is demonstrated with both PSpice simulations and experimental results.

Page segmentation is necessary for optical character recognition and very useful in document image manipulation. This paper describes two classification methods, a modified linear adaptive method and a proposed neural network system that classifies an image into text, halftone image (photos, dark images, etc.), and graphics (graphs, tables, flowcharts, etc.). The blocks were segmented using the Run Length Smearing Algorithm. The smearing process was done automatically by fixing the threshold values for smearing. Features are extracted from the segmented blocks for classification into text, graphics, and halftone images. The second method uses a multi-layer perceptron neural network for classification. Two parameters, a shape factor, f₁, and an angle from the rectangular block segments, were fed into the neural network system giving us three classes: text, halftone images, and graphics. Experiments on 30 mixed-content document images show that the method works well on a wide variety of layouts in document images.

Circuits for realizing floating capacitors using grounded capacitors and current conveyors are described. The effect of all the nonidealities of the various current conveyors on the realized impedances has been analyzed in detail.

In this letter an Improved Cell Search Design using cyclic codes (Improved CSD) is compared with the 3GPP Cell Search Design using comma free codes (3GPP-comma free CSD) in terms of (1) hardware utilization on a field programmable gate array and (2) acquisition time measures for different probabilities of false alarm rates. Our results indicate that for an additive white Gaussian noise channel in a high signal-to-noise ratio the Improved CSD achieves faster synchronization with the base station and has lower hardware utilization when compared with the 3GPP-comma free CSD scheme under the same design constraints.

FPGA-based emulation, which is now widely used in the design and verification of System-on-a-Chip (SoC), is applicable only when the RTL design for the whole system is available, thus resulting in a long design turn-around time. In this paper, we present a new design flow based on a C-to-hardware IMPLEmentation tool (CIMPLE) and a CONfigurable SoC Emulation Platform (CONSCEP) that emulates the on-chip bus system prior to the RTL design of each SoC component. With the emulation environment set up in the early stage of the design process, the design and verification task of each functional block in the SoC can be performed not only faster, but also more complete as a more complete set of test vectors can be applied before the integration. CONSCEP consists of (1) configurable bus components for the given on-chip bus standard and (2) a set of transactors to link the HDL models of the pre-verified IP blocks with the C models for the behavioral blocks to be designed, or software blocks. CIMPLE translates the C model for a hardware module to a SystemC code, which can be synthesized and directly attached to the CONSCEP as an IP. CIMPLE allows global variables, nested function calls, and simple pointer access, which significantly reduces the code migration. The proposed design flow is demonstrated using a JPEG encoder/decoder system and successfully applied to a commercial MPEG4 video codec chip.

A novel voltage-mode universal filter employing only two current differencing buffered amplifiers (CDBAs) is proposed. The filter uses four inputs and single output to realize six responses, viz. low-pass, high-pass, inverting band-pass, noninverting band-pass, band-elimination, and all-pass through input selection with independent pole-Q control. Computer simulation results using SPICE are also given to verify the theory.

FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.