Journal of Circuits, Systems and Computers

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).^1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

Negative impedance converter circuits (NICs) are important building blocks in design and manufacturing of analog and mixed mode integrated circuits. In this paper, a catalogue of single-current feedback amplifier-based negative impedance converter circuits having impedance scaling properties is proposed. Various examples are presented to illustrate the versatility of the proposed NIC circuits.

Variable gain Current Conveyors have been proposed to allow control of the value on fixed resistors. In this paper, procedures will be described, taking into account the stability of different configurations when a practical CCII^- is applied. Correction circuits will modify the control range. Frequency response and transients are shown.

The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

Over the past few years, scaling phenomena involving self-similarity and heavy-tailed distributions have attracted the interest of various researchers in telecommunications and networks. In this paper, we study the linear fractional stable noise (LFSN) which exhibits both long-range dependence and heavy tails property. LFSN can be represented as a linear process with weight coefficients and α-stable random variables. The coefficients of the linear process are determined by a kernel function and depend on five parameters. This paper focuses on estimating two unknown parameters a and b. Based on minimizing square errors, several methods for estimating these two parameters are presented. Detailed tables and graphs have been included in extensive simulations which show the methods are good estimates.

Reduction of search region in stereo correspondence can increase performances of the matching process, in the context of execution time and accuracy. For an edge-based stereo matching, we establish relationships between the search space and the parameters like relative displacement of edges, disparity under consideration, image resolution, CCD (Charge-Coupled Device) dimension and focal length of the stereo system. Then, we propose a novel matching strategy for the edge-based stereo. Afterward, we develop a fast edge-based stereo algorithm with combination of the obtained matching strategy and a multiresolution technique using Haar wavelet. Considering the conventional multiresolution technique using Haar wavelet, the execution times of our proposed method are decreased between 26% to 47% in the feature matching stage. Moreover, the execution time of the overall algorithms (including feature extraction and feature matching) is decreased between 15% to 20%. Theoretical investigation and experimental results show that our algorithm has a very good performance; therefore this new algorithm is very suitable for fast edge-based stereo applications like stereo robot vision.

This paper describes and analyzes a low-noise and high-bandwidth transimpedance amplifier featuring a large dynamic range. The designed amplifier is configured on three identical stages that use an active load compensated by an active resistor to improve the stability performance of the amplifier. This topology displays a transimpedance gain of 150 kΩ, which is necessary to obtain a high sensitivity. This structure operates at 5 V power supply voltage, exhibits a gain bandwidth product of 18 THzΩ and a low-noise level of about . This transimpedance amplifier can reach a transmission speed of 240 Mb/s for a photocurrent of 0.5 μA. For a photocurrent of 9.5 μA, a transmission speed of 622 Mb/s can be achieved by using an optical fiber connection containing four channels. The predicted performance is verified by simulations using PSPICE and MAGIC tools with 0.8 μm CMOS AMS parameters.

A new algorithm for reducing the division operation to a series of smaller divisions is introduced. Partitioning the dividend into segments, we perform divisions, shifts, and accumulations taking into account the weight of dividend bits. Each partial division can be performed by any existing division algorithm. From an algorithmic point of view, computation analysis is performed in comparison with the existing algorithms. From an implementation point of view, since the division can be performed by any existing divider, the designer can choose the divider which best meets his specifications. Although the algorithm is presented for integer numbers, it can be easily generalized for fractions, since it is only a matter of representation. Two possible implementations of the algorithm, namely the sequential and parallel are derived, with several variations, allowing performance, cost, and cost/performance trade-offs. Exhaustive comparisons of the derived implementations with many existing implementations in terms of area cost, performance, and cost/performance are done. A plethora of alternative implementations can be derived due to a variable number of partitions.

A generic model for second-order RC sinusoidal oscillators is derived. The model is based on treating an oscillator as a second-order passive network, with an arbitrary unknown structure, terminated at one port by a linear voltage-controlled negative resistor. A modified model which takes into account the fundamentally nonlinear characteristics of the negative resistor is also derived.

In this paper, we describe the Linear Matrix Inequality (LMI) approach to the analysis and the synthesis of continuous-discrete linear shift-invariant multidimensional systems presented in the Roesser form. We consider stability, stability margins, robust stability, stabilization and stabilization to the prescribed stability margins and robust stabilization. An example is included as illustrations of the obtained results.

So far, impulsive synchronization method has been applied to several well-known chaotic circuits and systems such as Chua's circuit, Lorenz system and hyperchaotic circuit. Here, we present a study of impulsive synchronization of another chaotic circuit, namely mixed-mode chaotic circuit which oscillates both autonomous and nonautonomous chaotic dynamics. By choosing two mixed-mode chaotic circuits as driving and driven chaotic circuits, we investigated whether these circuits are synchronized impulsively or not by evaluating the minimum length of impulse width (Q), and the ratio of impulse width to impulse period (Q/T). The results of our investigation confirm that two mixed-mode chaotic circuits can be synchronized impulsively with very narrow impulse width.

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

Digital scan conversion (DSC) is the process of converting received ultrasound signals, or echoes, in multi-scan lines, at varying angles (polar coordinate), to a Cartesian raster format for displaying. In this paper, we propose a new DSC technique that uses nearest-neighbor interpolation and the linear interpolation between adjacent scan lines to reduce artifacts on the far field, with smaller angular separation between the interpolated lines. A hardware implementation is described that uses only a FIFO register and a display memory. Rapid prototyping using an ARM processor with FPGA resources is achieved to validate the operation of the described system. Experimental results of the implemented design demonstrated the expected operation of the reduced complexity architecture in term of needed memory. Also, the performance of retrieved images were increased.

In the paper, we study the steady-state methods of large dynamic systems. For a nonlinear system of differential-algebraic equations with a known period T, we decouple it, in function space, into linear subsystems by quasilinearization. The resulting linear dynamic systems can be solved by a waveform Krylov subspace method. For the autonomous case, that is, the period T is unknown, the well-known shooting process can be applied where Newton iterations are computed with pseudo-inverse.

New classes of ternary linearly independent transforms as the bases of ternary polynomial expansions over GF(3) are introduced here. Recursive equations defining the linearly independent transforms and their corresponding butterfly diagrams are shown. Various properties and relations between the introduced classes of new transforms are discussed. Computational costs to calculate linearly independent transforms over GF(3) and applications of the corresponding polynomial expansions in ternary logic design are also presented.