Journal of Circuits, Systems and Computers

Due to its programmable threshold-voltage characteristic, the floating-gate MOS transistor (FGT) plays an important role in the low-power applications. To tune the threshold voltages of FGTs accurately, a real-time system is presented to measure the threshold voltages. The system includes decoders, analog multiplexers, threshold-voltage measurement block, A/D converter and 32-bit advanced RISC machine (ARM). The feedback technique is applied so that the threshold voltages of FGTs can be measured with high accuracy. The measurement error lies in the range of ±0.3% with 16-bit A/D converter, and there has no constraint on the choice of capacitances between floating-gate and control-gate. The proposed measurement system does not require any matched component. The mathematical models of threshold-voltage measurement block are also presented. Thus, the accuracy of threshold-voltage measurements can be verified with these models.

The parallel resonant scheme used to excite the magnets is characterized with high quality factor. The characteristic steep slope of the network gain near the resonant frequency makes the performance susceptible to the changes in component values. To accommodate the effect of varying component values, appropriate amplitude and phase over-drive capabilities in the ac source are required to maintain the magnet current of desired amplitude and in desired phase. A method of analysis of component tolerances using general purpose circuit simulation software, PSpice, is proposed in this letter. Using proposed normalized circuit description of the parallel resonant scheme, worst-case combination of component tolerances is determined. The evaluation of the effect of component tolerances in terms of required magnitude and phase over-drive of the ac source is presented under illustrative circuit conditions. Effect of various parameters on the over-drive is examined.

In this paper, an experimental study of practical realization to transmit private binary signals using chaos is presented. In particular, we use a Generalized Hamiltonian forms approach to synchronize two unidirectionally coupled Chua's circuits with the receiver being given by an observer. Experimental results are in close accordance with the numerical simulations.

Though, in most practical applications, the length of the adaptive filter is less than that of the unknown system impulse response, analysis of adaptive filtering algorithms almost always assumed a sufficient length adaptive filter whose length is equal to that of unknown system. Theoretical results on the sufficient length adaptive algorithm do not necessarily apply to the realistic insufficient length case and, therefore, it becomes extremely desirable for practical purposes that we quantify the statistical behavior of the insufficient length adaptive algorithm. In this paper, we analyze the popular Transform Domain LMS (TDLMS) algorithm with insufficient length adaptive filter for Gaussian input data and using the common independence assumption. Analysis yields exact theoretical expressions that describe the mean and mean-square convergence of the algorithm, which lead to a better understanding to the performance properties of the insufficient length TDLMS adaptive algorithm. Simulation experiments illustrate the accuracy of the theoretical results in predicting the convergence behavior of the algorithm.

The paper discusses complexity of circuit realization through Haar wavelet series. The efficiency in circuit synthesis using a method for minimization of the number of non-zero Haar coefficients by permutation of binary coordinates of indices of Haar functions is considered. Some applications of Haar wavelet transform and efficient ways of its calculation for logic domain are also discussed.

This paper presents a low-order and accurate method for the design of FIR fractional delay (FD) filters with complex coefficients. This method employs least square technique in Hilbert space to approximate the ideal FD transfer function with a FIR filter and to calculate its coefficients. The main advantages of the resulting filter are: very good response at all frequencies compared to other FD filter design methods and a good method to create very small delay. Design examples are presented to illustrate the effectiveness of this new design approach.

This letter presents a new architecture for othogonal variable spreading factor (OVSF) code generator. The basic idea of the proposed method is to generate the code sequence using the outputs of binary counter and the binary representation of the code number. The proposed architecture can generate the code sequences as adding the only combinational logic circuits without an additional counter, if other code sequences are required according to SFs. Since the proposed generator is applied to W-CDMA modem that used different SFs simultaneously, it contributes to the reduction of the modem hardware complexity.

Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

This paper proposes a symbolic reachability analysis method for multiple-clock system design, which is the first approach to deal with both synchronization problems caused by metastability and rate mismatch problems caused by clock frequency mismatches in a single framework. Three methods are described to reproduce problems that occur with multiple-clock system design during reachability analysis: (1) alternate evaluation for a system with two clocks as the base-line model, (2) nondeterministic delayed evaluation to reproduce a synchronization problem, and (3) double evaluation to reproduce a clock frequency mismatch. Experimental results on ISCAS 89 benchmark show an improvement factor of average CPU time as compared to Clarke's method by 1.29, 55.41, 2.19 and 45.23 times when alternate evaluation, double evaluation, alternate evaluation with NDDE and double evaluation with NDDE is applied, respectively.

In this paper, efficient pipelined architectures for the implementation of the Transform Domain LMS (TD-LMS) adaptive filter are considered. Pipelining of the TD-LMS algorithm is achieved by introducing an amount of time delay into the original adaptive scheme. The resulting algorithm, called thereafter the delayed TD-LMS, performs adaptive filtering with delayed coefficients adaptation. A statistical performance analysis of the proposed delayed TD-LMS adaptive algorithm is presented, both for the mean error and the mean squared error of the filter coefficients. A closed form expression is derived for the estimation of the steady state excess mean squared error, in terms of the adaptation delay and the input signal characteristics. The adaptation delay introduced to the delayed TD-LMS algorithm is subsequently utilized for the development of pipelined architectures. By retiming the delays existing in the error signal feedback loop, efficient pipelined implementations of the delayed TD-LMS algorithm are developed. The proposed architectures are suitable for parallel implementation on a general-purpose parallel machine, or on dedicated hardware, integrated on ASIC or ASIP VLSI processors.

A novel Discriminative Vector Quantization method for Speaker Identification (DVQSI) is proposed, and its parameters selection is discussed. In the training mode of this approach, the vector space of speech features is divided into a number of regions. Then, a Vector Quantization (VQ) codebook for each speaker in each region is constructed. For every possible combination of speaker pairs, a discriminative weight is assigned for each region, based on the region's ability to discriminate between the speaker pair. Consequently, the region, which contains a larger distribution difference between the speech feature vector sets of the two speakers in the speaker pair, plays a more important role by assigning it a larger discriminative weight, in identifying the better speaker match from the two speakers. In the testing mode, to identify an unknown speaker, discriminative weighted average VQ distortion pairs are computed for the unknown speaker input waveform. Then, a technique is described that figures out the best match between the unknown waveform and speakers' templates. The proposed DVQSI approach can be considered a generalization of the existing VQ technique for Speaker Identification (VQSI). The method presented here yields better Speaker Identification (SI) accuracy by employing the discriminative weights and space segmentation as design parameters. This is confirmed experimentally. In addition, a computationally efficient implementation of the DVQSI technique is given which uses a tree-structured-like approach to obtain the codebooks.

State encoding problem assigns binary codes to given symbolic states such that a specific objective function such as power dissipation can be optimized in the final implementation. In this paper, we present a novel encoding technique to minimize the switching activity of any given FSMs for low power design. The experiments with standard benchmarks show that the proposed algorithm is a significant improvement over previous ones.

In scalable CC-NUMA multiprocessors, it is crucial to reduce the average memory access time. For applications where the second-level (L2) cache is large enough, we propose a split L2 cache to utilize the surplus space. The split L2 cache is composed of a traditional LRU cache and an RVC (Remote Victim Cache) which only stores the data of remote memory address range. Thus, it reduces the average L2 cache miss time by keeping remote blocks that would be discarded otherwise. Though the split cache does not reduce the miss rates, it is observed to reduce the total execution time effectively by up to 27%.It even outperform an LRU cache of double size.

The present paper describes a converter where both series and parallel resonant circuits are used. In order to minimize losses, switching is made at zero current crossover (ZCS). The converter described in this paper has four MOS-controlled thyristor (MCTs) in H-bridge configuration (Full bridge). It is used for an induction cooking-range with two hot zones. The switching frequency is 50 kHz. To optimize the system efficiency, different control strategies are discussed.

The base-band section of a modem employing Orthogonal Frequency Division Multiplexing (OFDM) is described in this paper. It utilizes the necessary algorithms to combat distortion due to the channel conditions and imperfect synchronization. A model describing these distortions is used to derive the algorithms. The system is realized in a prototype platform for the HIPERLAN/2 standard, but modifications for compliance to other broadband digital broadcasting and wireless networking OFDM systems are proposed. The performance of the prototype base-band modem is described.