Journal of Circuits, Systems and Computers

Error correcting codes (ECCs) are commonly used as a protection against the soft errors. Single error correcting and double error detecting (SEC–DED) codes are generally used for this purpose. Such circuits are widely used in industry in all types of memory, including caches and embedded memory. In this paper, a new genetic design for ECC is proposed to perform SEC–DED in the memory check circuit. The design is aimed at finding the implementation of ECC which consumes minimal power. We formulate the ECC design into a permutable optimization problem and employ special genetic operators appropriate for this formulation. Experiments are performed to demonstrate the performance of the proposed method.

In the tolerance analysis of electronic circuits, the concept of set-valued function is often useful. In this paper, an efficient algorithm is proposed for finding all solution sets of nonlinear resistive circuits described by systems of nonlinear equations containing set-valued functions termed piecewise-trapezoidal (PWT) functions. By numerical examples, the effectiveness of the proposed algorithm is confirmed from various viewpoints. It is also shown that the proposed algorithm could find all solution regions to a system of 1000 PWT equations in practical computation time.

The realization of the Tow–Thomas (TT) circuit using the Operational Transresistance Amplifier (OTRA) is reviewed. The circuit employs two OTRA, and all passive elements are floating as the original Tow–Thomas circuit. The Current Conveyor (CCII) TT circuits are reviewed next. The progress in the realization of the TT circuit using CCII is demonstrated clearly by summarizing eight different circuits. One of the circuits has the advantage of very high input impedance using all grounded resistors and capacitors. The Differential Voltage Current Conveyor (DVCC) as the active building block in realizing the TT circuit is also considered. Finally, current mode TT circuits using balanced output CCII are summarized. Top Spice (level 49), simulation results using technology SCN 05 feature size 0.5 μm from MOSIS vendor: AGILENT are included to demonstrate the magnitude and phase frequency response of the TT circuits. Additional simulation results for the total power dissipation, total harmonic distortion, intermodulation IM3, input and output referred noise spectral densities are also included for comparison purposes.

In this paper, a novel circuit for realizing voltage-mode first-order and second-order all-pass filter responses as well as second-order notch filter response depending on the passive component choice, is presented. This circuit has high input impedance; thus, it is easy to cascade the introduced filter with other voltage-mode topologies. Also, it uses a single Variable Gain Current Conveyer — VGCCII and only grounded capacitors. SPICE simulation results based on 0.35 μm TSMC CMOS technology parameters are given to confirm the theory.

In this paper, a new frame rate up-conversion (FRC) using Backward Multiple Reference Frame Motion (BMRF) compensated interpolation (MCI) algorithm is proposed. The BMRF algorithm has been compared with two most common MCI methods, Temporal Linear (TLIN) and Bidirectional MCI (BID) used in FRC, in the aspect of PSNR, perceptual quality, and computational complexity. The simulation results clearly showed that BMRF presented a trade-off solution between computation and interpolation quality. By using simple weighted frame interpolation between multiple frames, it reduced computation rapidly while keeping similar interpolation quality when compared to the BID method. The simplicity of the BMRF algorithm made it suitable for either software or hardware implementation essential for real-time FRC applications.

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μm². The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

A novel channel estimation scheme based on superimposed training is proposed for multiple-input multiple-output multi-band orthogonal frequency division multiplexing ultra-wideband systems. The optimal training symbols are derived with respect to the least-square channel estimate mean square error. Simulation shows that the proposed scheme benefits much higher effective data throughput over the conventional method.

In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal V_DD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

A novel resistorless oscillator is presented. The proposed structure enjoys electronic tunability property with minimum number of active and passive components. This oscillator uses a current-mode (CM) active device and has properties of current mode circuits. The validity of the proposed circuit is verified by experimental results.

In this paper, a lattice ℓ-step ahead output uncertainty prediction algorithm is presented. The proposed prediction scheme is applicable to linear, stable, auto-regressive (AR) systems. The uncertainty predictors utilize the structure of the lattice filters. Subject to the saturation limits of the excitation signal, the measurement of the system output, and the a priori bounds of the reflection coefficients, the set of the feasible predicted output variables is computed. The suggested scheme is recursively computed over an ℓ-step ahead future time window, while the prediction uncertainty intervals are similarly computed over the lattice stages, regarding the forward and the backward prediction errors. Simulation results are presented that prove the efficacy of the employed lattice uncertainty predictors.

An efficient method to eliminate redundant frequencies present in one of the existing multi-frequency methods for analog fault diagnosis is proposed in this paper. First the two-dimensional fault dictionary is constructed where entries are gain signatures of all faults and frequencies. The faults belonging to the same quantization levels are numbered sequentially and a frequency that has an ambiguity set with the highest number faults is eliminated after verifying that there are no repetitions after the deletion of this frequency. In this manner, all frequencies are examined for deletion. Finally the test frequencies, which cannot be deleted, remain resulting in a minimal set of test frequencies of a network to isolate a given set of faults.

Another method proposes a technique, which generates more number of frequencies to isolate all the faults, if the test frequencies generated using the existing methods are not sufficient.

Memory is becoming one of the major power consumers in computing systems. Therefore, energy efficient memory management is essential. Modern memory systems employ sleep states for energy saving. To utilize this feature, existing research activities have concentrated on increasing spatial locality to deactivate as many blocks as possible. However, they did not count the unexpected activation of memory blocks due to cache eviction of deactivated tasks. In this paper, we suggest a software-based power state management scheme for memory, which exploits temporal locality to relieve the energy loss from the unexpected activation of memory blocks from cache eviction. The suggested scheme SW-NAP makes a memory block remain deactivated during a certain tick, which has no cache miss over the block. The evaluation shows that SW-NAP is 50% better than PAVM, which is an existing software scheme, and worse than PMU, which is another approach based on the specialized hardware by 20%. We also suggest task scheduling policies that increase the effectiveness of SW-NAP and they saved up to 7% additional energy.

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the V_TH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V).

Classification of the communication signals has seen under increasing demands. In this paper, we present a new technique that identifies a variety of digital communication signal types. This technique utilizes a radial basis function neural network (RBFN) as the classifier. Swarm intelligence, as an evolutionary algorithm, is used to construct RBFN. A combination of the higher-order moments and the higher-order cumulants up to eight are selected as the features of the considered digital signal types. In conjunction with RBFN, we have used k-fold cross-validation to improve the generalization potentiality. Simulation results show that the proposed technique has high performance for classification of different communication signals even at very low signal-to-noise ratios.