Journal of Circuits, Systems and Computers

This paper proposes an adaptive design of nonlinear feedback controllers for a class of complex nonlinear applications that have ill-defined mathematical models due to the effects of uncertainties and external disturbances. The design is aimed at estimating the uncertain parameters of the system while using a feedforward-like technique to cancel the effect of disturbances and unwanted nonlinearities. This is being achieved using a combination of state feedback and Lyapunov-based techniques that can guarantee the asymptotic stability of the closed loop system. The controller is synthesized such that it will follow the performance of a reference model via satisfying a certain criterion. The control law is demonstrated to be easily achievable for applications that can be modeled by low-order dynamics, e.g., industrial processes (level, flow, pressure, etc.) and some automotive applications (active suspension). The key factor in the design is arriving at the best parameter update law that guarantees both stability and satisfactory transient performance. The application of the proposed controller is extended to higher-order systems via proposing a low-order nonlinear model that is capable of encapsulating the dominant dynamics of the system without using linearization techniques. Trade-offs between stability and performance are carefully studied along with comparisons with a nonmodel-based PID controller to highlight the superiority of the proposed design. A simulated nonlinear Duffing oscillator and a continuous stirred tank reactor are used to exemplify the suggested technique. Finally, a conclusion is submitted with comments regarding feasibility of the controller along with its advantages and limitations.

A new log-domain building block for log-domain filter design is proposed in this paper. This block realizes a positive impedance inverter (gyrator) by using the log-domain wave method. A simple procedure for log-domain filter development, using the proposed block, is outlined. This method results in circuits, which are simple in structure and very easy to design. An example of a second-order bandpass filter is given and its functionality is verified through simulations.

Having more hidden units than necessary can produce a neural network that has a poor generalization. This paper proposes a new algorithm for pruning unnecessary hidden units away from the single-hidden layer feedforward neural networks, resulting in a Spartan network. Our approach is simple and easy to implement, yet produces a very good result. The idea is to train the network until it begins to lose its generalization. Then the algorithm measures the sensitivity and automatically prunes away the most irrelevant unit. We define this sensitivity as the absolute difference between the desirable output and the output of the pruned network. Unlike other pruning methods, our algorithm is distinct in calculating the sensitivity from the validation set, instead of the training set, without increasing the asymptotic time complexity of the back-propagation algorithm. In addition, for a classification problem, we raise a point that the sensitivities of some well-known pruning algorithms may still underestimate the irrelevance of hidden unit even though the validation set is used in measuring the sensitivity. We resolve this problem by considering the number of misclassified patterns as the main concern. The Spartan simplicity algorithm is applied to three artificial and seven standard benchmarks. In most problems, the algorithm can produce a compact-sized network with high generalization ability in comparison with other pruning algorithms.

Motion-JPEG2000 is derived from Part 1 of the JPEG2000 standard and provides high quality image compression in video coding system. This paper presents a real-time Motion-JPEG2000 encoding which is built on a fixed-point digital signal processor (DSP) as a single-chip implementation. The design addresses on the system-level design considerations. Among several modules in JPEG2000, Embedded Block Coding with Optimized Truncation (EBCOT) algorithm contains the highest computation complexity and also becomes the bottleneck of JPEG2000. Two speed-improved methods are proposed to significantly reduce the processing time of EBCOT. The fast algorithm is used by processing the three coding passes in sequential and is very suitable to the execution on programming-based processor. For Motion-JPEG2000 implementation, a real-time encoding system is built on the single-chip DSP processor without any extra hardware support. The optimization techniques are also applied to enhance the performance. Due to the contribution on algorithm and implementation issue, the complexity of Motion-JPEG2000 is largely reduced. Simulation results show that the proposed system can process 30 frames per second in CIF size (352 × 288 pixels) with 4:2:0 video sequences. For SDTV size resolution (760 × 480 pixels), the system can achieve near 20 frames per second.

Based on a recent market study of an important number of I²C devices, all fully compliant with the Philips I²C-bus specification, version 2.1, release January 2000, this paper introduces a detailed I²C-slave VLSI-architecture that incorporates all necessary features required by modern ASIC/SoC applications, except high speed mode. The design is a general purpose solution offering viable ways to controlling I²C-bus and highly flexible to suit any particular needs.

The purpose of this paper is to provide a full description of an up-to-date I²C-slave FPGA implementation. All related issues, starting from the elaboration of initial specifications, till the final verifications and synthesis, are comprehensively discussed and justified. This includes all issues from basic architectural operations to final software drivers and application.

The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365). The synthesis design code is technology independent and was simulated at both RTL and gate level with timing back annotation using ModelSim SE 5.8e and synthesized using both Leonardo Spectrum V2001_1d.45 and Xilinx's XST 6.1i.

The sensor placement problem for complete information coverage in a distributed sensor network is studied. Sensors are assumed to be placed on the grid points of a grid in the sensor field and complete information coverage is claimed if all the grid points are information covered. This sensor placement problem is formulated as a constrained optimization problem where the objective is to minimize the total cost while guaranteeing certain coverage requirement. We propose a greedy algorithm to solve this problem. Computational results show that the proposed algorithm can efficiently obtain a good quality solution with greatly reduced computation complexity and the number of sensors can be greatly reduced for information coverage.

The history of Kerwin–Huelsman–Newcomb (KHN) second-order filter is reviewed. A generation method of the KHN filter from passive RLC filter is presented. Two alternative forms of the KHN circuit using operational amplifier are reviewed. The effect of finite gain-bandwidth of the op amps is considered and expressions of the actual ω₀ and Q are given. Two KHN circuits with inherently stable Q factor are also included. Two new partially compensated inverted KHN circuits are introduced. Active compensation methods to improve the KHN and the inverted KHN circuit performance for high Q designs are summarized. Spice simulation results are given. The progress of the KHN realizations using the current conveyor is also summarized briefly.

The objective of this short report is to present an intuitive methodology on second-order dynamic oscillator design based on divergence and curl vectorial calculus operations.

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.

Multi-rate controllers are useful in providing fast control updates using slow measurements. The multi-rate control loop involves up-sampling, down-sampling, and systems considered at different timescales. The challenge is then, to present complete frequency domain model of the loop. This paper presents the frequency domain model of the loop which is suitable for analysis and design of controllers. The approach is illustrated through a numerical example.

This paper presents a second-order bandpass filter for IF frequencies in the range of 500 kHz–2 MHz. By using a single G_m–cell as a biquad filter, considerable saving in area and power is feasible. Higher order structures can be achieved by cascading this second-order block. This G_m-C filter achieves a dynamic range of 37 dB for 1% IM3 in Bluetooth while dissipating only 10.5 mW from 3.3 power supply in 0.35 μm CMOS process. The on-chip indirect automatic tuning circuit sets the filter center frequency to an external reference clock.

The complexity of modern embedded systems requires a revised and systematic approach to efficient and concurrent management of hardware (HW) and software (SW) parts in a codesign process. In order to optimally meet the ever-increasing design requirements and at the same time leverage design productivity, higher level aspects need to be addressed before worrying about the HW/SW boundary. This paper deals with high-level aspects of system-level modeling and provides modeling extension, from which contemporary related methodologies can greatly benefit. High-level aspects, their influence on the entire design flow, and systematic integration into the codesign environment are presented. An approach is proposed with a higher level of abstraction that helps bridge the gap between informal and formal system specifications. Higher level design decisions are enabled, avoiding premature ad hoc design decisions. Applicability of the proposed high-level codesign concepts is illustrated with a case study.

New type of m-ary systolic arrays called reversible systolic arrays is introduced in this paper. The m-ary quantum systolic architectures' realizations and computations of the new type of systolic arrays are also introduced. A systolic array is an example of a single-instruction multiple-data (SIMD) machine in which each processing element (PE) performs a single simple operation. Systolic devices provide inexpensive but massive computation power, and are cost-effective, high-performance, and special-purpose systems that have wide range of applications such as in solving several regular and compute-bound problems containing repetitive multiple operations on large arrays of data. Similar to the classical case, information in a reversible and quantum systolic circuit flows between cells in a pipelined fashion, and communication with the outside world occurs only at the boundary cells. Since basic PEs used in the construction of arithmetic systolic arrays are the add–multiply cells, the results introduced in this paper are general and apply to a very wide range of add–multiply-based systolic arrays. Since the reduction of power consumption is a major requirement for the circuit design in future technologies, such as in quantum computing, the main features of several future technologies will include reversibility. Consequently, the new systolic circuits can play an important task in the design of future circuits that consume minimal power. It is also shown that the new systolic arrays maintain the high level of regularity while exhibiting the new fundamental bijectivity (reversibility) and quantum superposition properties. These new properties will be essential in performing super-fast arithmetic-intensive computations that are fundamental in several future applications such as in multi-dimensional quantum signal processing (QSP).