Journal of Circuits, Systems and Computers

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

A new generation method of the Tow-Thomas (TT) circuit based on the nodal admittance matrix (NAM) expansion is given. The family of TT circuits defined includes four different types of generated circuits. All the advantages of the classical TT circuit namely, independent control on the frequency, selectivity factor Q and gain, besides having very low passive sensitivities are maintained. Besides, each of the family members of the generated circuits use grounded passive elements and has very high input impedance. It is found that there are eight circuits in each type implying a total of 32 TT circuits using current conveyors (CCII) and inverting current conveyors (ICCII). 24 circuits are new and four of them have a floating property.

In this paper, we describe a new algorithm for radar detection based on the Hough transform which employs the slope-intercept parameter space. Unlike the conventional Hough transform, we shift the parameter space cells to perform the transform. The computation burden is reduced. Another advantage is that those straight lines whose intercept are bigger than the radar maximum range can also be detected. In addition, we also investigate the performance of the algorithm we present and show its efficiency with some simulations.

The study presented in this paper highlights an important issue that was subject for discussions and research about a decade ago and now have gained new interest with the current advances of grid computing and desktop grids. New techniques are being invented on how to utilize desktop computers for computational tasks but no other study, to our knowledge, has explored the availability of the said resources. The general assumption has been that there are resources and that they are available. The study is based on a survey on the availability of resources in an ordinary office environment. The aim of the study was to determine if there are truly usable under-utilized networked desktop computers available for non-desktop tasks during the off-hours. We found that in more than 96% of the cases the computers in the current investigation was available for the formation of part-time (night and weekend) computer clusters. Finally we compare the performance of a full time and a metamorphosic cluster, based on one hypothetical linear scalable application and a real world welding simulation.

Differential Voltage Current Feedback Operational Amplifiers (DVCFOAs) and conventional CFOAs are employed as active elements for designing leapfrog filters in this work. DVCFOAs are realized by enhancing the topology of the conventional CFOA in order to have available a second high-impedance input terminal and, simultaneously, establishing a voltage at low-impedance input terminal equal to the difference between the voltages at high-impedance input terminals. A third-order leapfrog filter is realized by employing CFOAs or DVCFOAs, and the most important performance factors of the corresponding configurations have been considered in order to investigate the benefits offered by each topology.

A pulse-current converter topology for induction heating is simulated and implemented. The possibility and expediency of the pulse current for induction heating have been demonstrated. The converter comprises the input filter, input reactor, bridge rectifier, two power switches, two coils mutually coupled with the input reactor and the heating inductor (load), where the output power is controlled by a switching frequency. The steady-state analysis of the converter operation and its computer simulation has been performed. The simulation on the computer are shown to be in good agreement with the theoretical results. The following two goals have been achieved: (a) the analysis of the heating process with the pulse current has been performed; and (b) the appropriate scheme of the pulse-current supply has been developed. The scheme fulfills the requirements of modern power supplies: sine form of the input current, unity power factor, soft commutation and a wide range of output power. This configuration can be used for heating, annealing, melting and hardening in the power range of 250–300 kW.

The admittance matrix expansion method based on using nullors and pathological mirror elements is used to provide a systematic synthesis method of controlled sources. Four new realizations of the current controlled voltage source (CCVS) using a single grounded resistor are given. Three new nodal admittance matrix expansions (NAM) for the voltage controlled voltage source (VCVS) are introduced in this paper. The voltage mirror current mirror pair is used as intrinsic element in the NAM expansion. Eight new realizations for the noninverting VCVS using two grounded resistors are given. Eight realizations for the inverting VCVS using two grounded resistors are also given. Two new NAM expansions for the current controlled current source (CCCS) are introduced in this paper. The voltage mirror current mirror pair is used as an intrinsic element in the NAM expansion. Eight realizations for the CCCS using two grounded resistors are given. The generation of the controlled sources using a single building block is also discussed and the adjoint relations between VCVS and CCCS are summarized.

This paper presents a new design of half-static clock-gating D-type flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 μm CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures.

Advance in semiconductor technologies enables seamless integration of hundreds of cores on a single silicon die, which requires high communication performance. To deal with the increasing communication complexity of System-on-Chip (SoC), Network-on-Chip (NoC) has been recently proposed as an alternative to the conventional point-to-point links and bus based communication fabrics. In practice, to facilitate NoC design evaluation and optimization, Poisson traffic or Bernoulli traffic models are generally assumed. However, actual measurements showed that real high speed network traffic always has strong correlations. The objective of this paper is to investigate the impact of traffic correlations on the performance of NoC design. Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.

An all-optical data comparator with the help of Terahertz Optical Asymmetric Demultiplexer (TOAD) is proposed. The paper describes the all-optical data comparator by using a set of all-optical full-adder and optical switch. Comparison between two binary data is required in many data processing systems. It is sometimes necessary to know whether a binary number is greater than, equal to, or less than another number. The all-optical data comparator can be used to perform a fast central processor unit using optical hardware components. In this present communication, we have tried to exploit the advantages of TOAD-based switch to design an integrated all-optical circuit which can perform data comparison operations.

A new bandwidth estimation method based on the application of Miller theorem to single and multistage common source amplifiers is presented. This new method provides more accurate bandwidth estimation and circuit design insight than the traditional Miller, Elmore and open circuit time constant approaches.

In this paper, four instrumentation amplifier (IA) topologies, one of which is current-mode (CM) while the others are voltage-mode (VM), are presented. Three of the IAs use one to two current feedback operational amplifiers (CFOAs) while the other one employs only a single NMOS transistor. One of the IA circuits, given as an example, is simple while others are novel. The CM IA is composed of only grounded resistors which have some advantages in integrated circuit (IC) process. Non-ideality effects such as non-ideal gain and parasitic impedances on the performance of introduced IAs are discussed. In order to show the performance of the circuits, we perform experimental tests and simulations by using SPICE program.

Partial re-configuration is the process of configuring a portion of a FPGA while the rest of the device is still running/operating. This paper proposes a novel allocation methodology for realizing applications with partial and dynamic features on FPGAs. The methodology was implemented as a manager that incorporates two stages: the first one modifies the configuration data of each partial bitstream by replacing the associated application's functionalities (or slices), its goal being to compact the slice distribution, while keeping the same functionality. The second one determines the appropriate spatial location over the FPGA device where the previously optimized configuration data should be placed. The proposed manager is device independent, since it derives partial configuration data that can program dynamically any island-style or hierarchical FPGA. For demonstration purposes, the proposed manager was implemented as part of an existing bitstream generator tool, named DAGGER (part from the MEANDER framework) targeting to Virtex-like architectures.

Selective harmonic elimination pulse width modulation (SHE-PWM) techniques offer a tight control of the harmonic spectrum of a given voltage waveform generated by a power electronic converter along with a low number of switching transitions. These optimal switching transitions can be calculated through Fourier theory, and for a number of years quarter-wave and half-wave symmetries have been assumed when formulating the problem. It is shown recently that symmetry requirements can be relaxed as a constraint. This changes the way the problem is formulated and different solutions can be found without a compromise. This paper reports solutions to the switching transitions of a bipolar SHE-PWM when both the quarter- and half-wave symmetries are abolished. Selected simulation and experimental results are reported to show the effectiveness of the proposed method.