Journal of Circuits, Systems and Computers

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

Multiplexers are extremely important parts of signal control systems. Some critical circuits of computing systems, like memories, use large multiplexers in order to present the value of a specific memory cell to their output. Several quantum-dot cellular automata (QCA) circuits have been designed and the need for a QCA memory access system becomes prominent. A modular 2ⁿ to 1 QCA multiplexer covering small area could reduce the size of such circuits and conclusively could increase circuit integration. In this paper we present a novel design of a small size, modular quantum-dot cellular automata (QCA) 2ⁿ to 1 multiplexer that can be used for memory addressing. The design objective is to develop a modular design methodology which can be used to implement 2ⁿ to 1 multiplexers using building blocks. For the QCA implementation a careful consideration is taken into account concerning the design in order to increase the circuit stability.

Efficient co-channel and adjacent channel interference rejection is often one of the most demanding requirements for wireless receivers. Independent Component Analysis (ICA) has been previously applied to realize interference suppression. In particular, the fixed-point FastICA and complex FastICA algorithms can successfully perform blind signal extraction for real and complex valued communication signals in stationary or slow fading environments. Both algorithms exhibit fast convergence speed and impressive accuracy due to their Newton type fixed-point iteration. However, under dynamic channel conditions often encountered in practice, the fixed-point algorithms' performance is significantly degraded. In this contribution, a novel complex block adaptive ICA algorithm and its simplified real version is proposed, that overcome this limitation for the separation of complex valued and real signals with known source distributions. The new methods exploit prior information about the modulation scheme of the communication signals of interest, and achieve improved interference suppression performance in dynamic channel environments. The proposed complex ICA algorithm is called Complex Optimum Block Adaptive ICA (Complex OBA-ICA), and its abridged version for separating real signals is called General Optimum Block Adaptation ICA (GOBA-ICA). The proposed methods are applied to interference rejection in linearly and abruptly flat fading dynamic environments for diversity QPSK and BPSK wireless receivers. Simulation results show that the presented techniques demonstrate better convergence properties and accuracy as compared to the complex FastICA and FastICA algorithms.

In this paper, a CMOS current controlled current differencing buffered amplifier (C-CDBA) realization is presented. Also, a new first-order all-pass filter that compensates for some C-CDBA non-idealities is given as an application example. The all-pass filter circuit has low output impedance for easy cascadability and it can be made electronically tunable using the proposed C-CDBA implementation. The theoretical results are verified with SPICE simulations.

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-V_P-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

Memristor had been first theorized nearly 40 years ago by Prof. Chua, as the fourth fundamental circuit element beside the three existing elements (Resistor, Capacitor and Inductor) but because no one has succeeded in building a memristor, it has long remained a theoretical element. Some months ago, Hewlett-Packard (hp) announced it created a memristor using a TiO₂/TiO_2-X structure. In this paper, the characteristics, structures and relations for the invented hp's memristor are briefly reviewed and then two general SPICE models for the charge-controlled and flux-controlled memristors are introduced for the first time. By adjusting the model parameters to the hp's memristor characteristics some circuit properties of the device are studied and then two important memristor applications as the memory cell in a nonvolatile-RAM structure and as the synapse in an artificial neural network are studied. By utilizing the introduced models and designing the appropriate circuits for two most important applications; a nonvolatile memory structure and a programmable logic gate, circuit simulations are done and the results are presented.

A formula for point addition in elliptic curves using affine representation and its implementation in FPGA is presented. The use of this new formula in hardware implementations of scalar multiplications for elliptic curve cryptography has the main advantages of: (i) reducing area for the implementations of elliptic curve point addition, and (ii) increasing the resistance to side channel attacks of the hardware implementation itself. Hardware implementation of scalar multiplication for elliptic curve cryptography using this new formulation requires low area resources while keeping high performance compared to implementations using projective coordinates, which are usually considered faster than the affine coordinates.

In this paper, we present a genetic algorithm (GA) based methodology for vector generation that maximizes the metric of datapath coverage for a given combinational logic circuit, and compare it with a standard greedy algorithm. The search of maximum coverage vectors is a complex optimization of a satisfiability problem. The GA deals with the optimization problem, whilst an external satisfiability solver is invoked to deal with the coverage problem. Experimental results and performance comparisons based on the large set of MCNC'91 suite of benchmark circuits are presented. They show significant speedups of the GA methodology against a greedy algorithm for large circuits.

In this paper, a novel watermarking technique based on parametric slant-Hadamard transform is presented. Our approach embeds a pseudo-random sequence of real numbers in a selected set of the parametric slant-Hadamard transform coefficients. By exploiting statistical properties of the embedded sequence, the mark can be reliably extracted without resorting to the original uncorrupted image. The presented method is capable of increasing the flexibility of the watermarking scheme, where the changes in parameter set help to improve fidelity and robustness against a number of attacks. Experimental results show that the proposed technique is secure and indeed highly robust to these attacks.

With the increase of the complexity of circuits, fast estimation can provide some vital information for optimal layout decisions. Fast congestion prediction plays an important role in the physical layout of VLSI design. In this paper, we present a probabilistic estimation approach with via minimization constraints. Our model is more realistic than previous models. It has more flexibility for wires to have more usage area to bypass congested regions and blockages. The experiment on routing benchmarks demonstrates the effectiveness of our approach.

In this paper, a novel image watermarking scheme based on a self-reference technique is proposed. The meaningful watermark is embedded into a gray-level image according to the relation between the constructed reference image and the original host. In order to be robust against Jpeg compression, the reference image should be robust under Jpeg compression. Firstly, the original image is transformed into DCT domain; and then most of the high frequency coefficients are omitted; after the quantization step and inverse DCT transform, we can obtain a robust reference. By considering the relation between the original image and its reference, we can embed the watermark into the host. The watermark extraction process is oblivious. Experimental results under several attacks show good robustness of the proposed scheme. Especially under cropping and Jpeg compression attacks, the watermark can be extracted with only few errors.

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case M = 2). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers.