Journal of Circuits, Systems and Computers

We designed and tested a novel field-programmable gate array (FPGA)-based embedded system that uses automatic censored ordered statistics detector (ACOSD) algorithms to detect targets in clutter with lognormal distribution. The detection process operates through two techniques called backward and forward ACOSD (B-ACOSD and F-ACOSD, respectively), which work in parallel to increase the detection accuracy and reduce the false alarm rate. Two architectures were considered for the proposed detector. The B-ACOSD algorithm operates the censoring beginning from the last cell belonging to a window of N range cells, whereas the F-ACOSD algorithm considers the censoring based on a scan beginning with the first cell in the same sorted window of cells. The detector is implemented on a FPGA-Altera Stratix II as a system-on-chip that integrates a Nios II core processor with our proposed detector as a co-processor and additional embedded memories and interfaces using parallelism and pipelining. For a reference window of 16 cells, the processor works properly with a processing speed of up to 129.13 MHz and a processing time of only 0.23 μs, within the range of the maximum tolerated delay of 0.5 μs fixed by the pulse width [A. Farina, A. Russo and F. A. Studer, IEE Proc. F Commun. Radar Signal Process.133 (1986) 39–54] for viewing a target at high resolution.

In this paper, an ultra-wide band 0.18 μm CMOS common-gate low-noise amplifier (LNA) is presented. Designed in the ultra-wide band frequency range of 3.1–10.6 GHz, it uses a current-reused technique with modified input matching. This approach allowed obtaining a flat broadband gain of 12.75 ± 0.83 dB with an input reflection coefficient less than -5.5 dB, an output reflection coefficient less than -7 dB, and a noise figure less than 3.7 dB. Furthermore, the proposed low-power LNA consumes only 12.14 mW (excluding buffer) from a 1.2 V supply voltage.

This paper presents an active-RC continuous time filter in 0.18 μm standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 μW.

This paper deals with the flux detection of squirrel cage induction generator (SCIG) in wind power. A novel observer named impulsive observer is presented to estimate the states of SCIG. Conditions for the existence of the impulsive observer are established by using linear matrix inequalities. A realization for the observer in SCIG is proposed. Simulation results are provided to show the validation of the proposed method.

In this paper, a frequency-tunable dynamic pulse integrating circuit for infrared receivers is presented. The proposed circuits possess many advantages, such as high sensitivity, high immunity against disturbances, simple structure, and so on. This integrator not only defines a minimum time for the burst length and a minimum time between the bursts, but also achieves the same minimum number of pulses in different frequencies. The frequency-tunable dynamic pulse integrator is a combined structure of the center frequency modulation and a new type of pulse integrator. The center frequency modulation is implemented by using zener zap anti-fuse trim and a second-order band-pass filter (BPF) with bipolar operational transconductance amplifier (OTA) cell. The integrator also describes the characteristics of variable-error tolerance to prevent the output envelope error due to the lack of individual pulses. The results of simulation are shown that the center frequency is available from 33 to 40 kHz and 56 kHz in typical application by Cadence respectively. Moreover, the minimum burst length is 10 pulses and minimum bursts gap time is 14 pulses in typical application.

This paper reports a refined multi-tone waveform measurement system for the robust characterization and optimization of nonlinear microwave devices when driven by broadband multi-tone stimuli. This enhanced system has the ability to present specific, constant broadband impedances, not only at baseband (IF) frequencies, but also at RF frequencies, particularly, around the carrier and significant harmonics. This functionality is key in studying the effects of out-of-band impedance termination on both short and long-term electrical memory effects. Achieving such comprehensive impedance control across wide modulation bandwidths is also critical in allowing the "emulation" of emerging power amplifier modes and architectures, and the subsequent waveform characterization of devices operating in these complex and often dynamic impedance environments. Initially, the baseband load-pull capabilities of the enhanced measurement system are experimentally demonstrated through the measurement of adjacent channel power (ACP) behavior of a class AB biased 10 W GaN HEMT, in response to a varying baseband load. Complete baseband and RF impedance control is then demonstrated through the emulation and analysis of a modulated Class-J impedance environment, which interestingly highlights the presence of separate optimum baseband impedance conditions necessary for the suppression of individual IM products.

The paper presents new approach to the analysis of the time required for rendering, depending on the complexity of the 3D object. Ray tracing is used to measure program complexity measure parameter based on the rendering time. Parametric analysis using ray tracing program is achieved by correlation between image parameters and rendering time. Electronic imaging and image processing (rendering) are considered in the 3D virtual photorealistic imaging design and electronic imaging creation and optimization. We are attempting to treat the complexity as a measure in the process of creating and rendering a complex image. The work is directed towards defining and optimizing the rendering time in the photorealistic 3D image creation process. The correlation between large numbers of image components obtained by the ray tracing program is used to measure the scene complexity regarding of render time. To discover which space variable to use as complexity measure, we cross-correlated variables output by ray tracing program, keeping track of the maximum values. Based on this method, the highest correlation was observed on variable Bounding box succeeded tests, and that way obtained the complexity measure for the image. That way the original research is performed in creating analytical (data-visual) methods for determining the image rendering parameters. The results based on experimental verification on a large number of performed standard tests on real sets of graphical contents, and established the impact of graphical content complexity to the rendering time at distributed cluster computing systems.

As semiconductor technologies scale down to deep sub-micron dimensions, transient faults will soon become a critical reliability concern. Due to their prohibitive costs, traditional high-end solutions are unacceptable for the mainstream commodity market. This paper presents FTPIPE, a hybrid software/hardware solution, which provides sufficient fault coverage with affordable overhead for single-threaded programs running on commodity systems. Leveraging existing exception mechanisms with minor modifications to handle exception-causing faults, FTPIPE focuses on tolerating silent data corruptions by using compile-time analysis and performing selective instruction replication in a modern superscalar pipeline extended with minimal hardware overhead. Unlike existing instruction replication-based solutions, which detect faults by synchronous checks, the FTPIPE platform has exploited a novel hybrid synchronous/asynchronous check method for the replicated instructions. In this manner, better performance can be obtained without degradation of fault coverage. By synchronous checks, the validation of the result of a replicated instruction must be finished before it is committed, whereas such a guarantee is not required by an asynchronous check. Evaluation using a set of nine programs from the Mibench benchmark suite demonstrates that FTPIPE can tolerate 89.8% of transient faults under a modest performance overhead of 20.1%.

This paper introduces chaotic reference model-based dynamical state feedback chaotification method which can be applied to any input-state linearizable (nonlinear) system including linear controllable ones as special cases. In the developed method, any chaotic system of arbitrary dimension can be used as the reference model with no need to transform it into a special form, so providing the advantage of exploiting the vast amount of information on chaotic systems and their implementations available in the literature. To demonstrate the potential effective applications of the method, a permanent magnet dc motor is chaotified by the proposed dynamical state feedback as matching the closed loop dynamics to the well-known Chua's chaotic circuit. Then, an impeller mounted on the chaotified dc motor is used for mixing a corn syrup added acid–base mixture. It is observed in a nonintrusive way that mixing actuated by the chaotified dc motor is more efficient than constant and also periodical motor speed cases for the consideration of neutralization time and power consumption together.

A systematic synthesis procedure for generating third-order grounded passive element quadrature oscillators is given. The synthesis procedure is based on using nodal admittance matrix (NAM) expansion applied to the Y matrix of a recently reported three Op Amp third-order oscillator circuit. Four new circuits using current conveyors (CCII) are reported. In addition four more new circuits using inverting current conveyors (ICCII) are also given. Many more quadrature third-order oscillator circuits using combinations of CCII and ICCII can be obtained. Simulation results demonstrating the practicality of one of the generated circuits are included.

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.