Journal of Circuits, Systems and Computers

An area-efficient high-throughput shift-based LDPC decoder architecture is proposed. The specially designed (512, 1,024) parity-check matrix is effective for partial parallel decoding by the min-sum algorithm (MSA). To increase throughput during decoding, two data frames are fed into the decoder to minimize idle time of the check node unit (CNU) and the variable node unit (VNU). Thus, the throughput is increased to almost two-fold. Unlike the conventional architecture, the message storage unit contains shift registers instead of de-multiplexers and registers. Therefore, hardware costs are reduced. Routing congestion and critical path delay are also reduced, which increases energy efficiency. An implementation of the proposed decoder using TSMC 0.18 μm CMOS process achieves a decoding throughput of 1.725 Gbps, at a clock frequency of 56 MHz, a supply voltage of 1.8 V, and a core area of 5.18 mm². The normalized area is smaller and the throughput per normalized power consumption is higher than those reported using the conventional architectures.

A new high figure-of-merit (FOM) and low-phase-noise 20.73-GHz voltage-controlled oscillator is designed for K-band applications in this paper. The capacitive feedback technique is used for the low-phase-noise VCO design. The VCO can be tuned from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding FOM is calculated to be -190 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one-poly-six-metal 1.7 V mixed-signal/RF CMOS technology, and the chip size is 0.51 × 0.74 mm².

The reliability of power distribution network is important. For high reliability, it is necessary for some nodes to have backup connections to other feeders in the network. The substation operator wants to expand the network such that some nodes have k redundant connection lines (i.e., k redundancy) in case the current feeder line does not work. The corporation is given this task to design the expansion planning to construct new connection lines. The substation operator will choose the minimum charged k redundant connection lines based on both of the existing network and the expansion network, which is designed by the corporation. The existing network has the cost for the redundant connection due to the operational expense. The corporation proposes the design with its own price, which may include the operational expense and the construction expense. Thus, for the corporation, how to assign the low price on the connection lines while maximizing the revenue becomes a Stackelberg minimum weight k-star game for the power distribution network expansion.

A heuristic algorithm is proposed to solve this Stackelberg minimum weight k-star game for the power distribution network expansion, using three heuristic rules for price setting in a scenario by scenario fashion. The experimental results show that the proposed algorithm always outperforms the greedy algorithm which is natural to k-star game in terms of corporation revenue. Compared to the greedy algorithm, the proposed algorithm improves up to 60.7% in the corporation revenue in the chosen minimum weight k-star, which is the minimum charged k connection lines. The average improvement is 7.5%. This effectively handles k redundancy in the power distribution network expansion while maximizing the corporation revenue.

A multi-integration technology with compact readout method to extend CMOS image sensor's dynamic range is presented. Compared with the timing of rolling readout, compact readout extends the available pixel readout time by adjusting the time-domain offset between two adjacent rows and each integration time in one frame. Thus the column readout bus is working continuously rather than intermittently, which makes good use of the whole integration time and the available readout time can be extended. This dynamic range extension technology was implemented on a prototype chip with a 128 × 128 pixel array. The pixel readout time with compact readout method is almost as 3 times long as the one with rolling readout method while 39 dB dynamic range extension is achieved at 120 fps.

Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number adders where m = 2ⁿ + μ(μ = ±1, 0). To simplify the residue SD adder, new addition rules are used for generating the intermediate sum and carry with an 1-bit binary encoded number representation. By using the new encoding method, the proposed residue addition requires less hardware and shorter delay time than previous one. A modulo m multiplier can be implemented by a binary modulo m adder tree which has a depth of log₂ n. In order to introduce a binary SD adder tree with the new addition rules, two novel modulo m adders have been proposed in this paper. Finally, the evaluation apparently shows that the proposed two kinds of modulo m adders are performed more efficiency by comparing with the modulo SD adder which is mentioned in our previous work, and a new binary SD adder tree structure has been proposed.

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.

The background that underlies this work is the envisioned real-time tele-immersive collaboration system for the future that supports delay-sensitive applications involving participants from remote places via their collaboration spaces (CSs). The end-to-end delay as high as 20 ms is required for good synchronization of such applications, for example collaborative dancing and remote conducting of choir. It is much lower than that facilitated by existing teleconference systems. A novel network architecture with delay guarantee, namely Distributed Multimedia Plays (DMP), has been proposed and designed to realize the vision. The maximum low latency is guaranteed because DMP network nodes can drop DMP packets of multimedia data from the CSs due to instantaneous traffic condition. Besides ultrafast processing time, modularity, and scalability must be taken into account in hardware design and implementation of the nodes for seamless incorporation of the modules. These lead us to employing field-programmable gate array (FPGA) due to its substantial computational power and flexibility. This paper presents an FPGA-based platform for the design and implementation of DMP network nodes. It provides a detailed introduction to the platform architecture and the simulation-implementation environment for the design. The modularity of the implemented node is shown by addressing three important modules for packet dropping, 3D warping, and image transform. Our compact implementation of the network node on Xilinx Virtex-6 ML605 mostly consumes very small amount of available resources. Moreover the elementary operations on our implementation takes (much) less than 5 μs as desired to meet the low-latency requirement.

The paper proposes a unified switch model for the analysis of circuits with ideal switches. The model is unique and valid for all states of switches. The developed model is based on modified nodal analysis (MNA) that exploits an efficient algorithm developed for linear active circuits. The analysis with the new switch model requires only one topology and uses the uniform system equations regardless of states of switches. The system equations and the states of switches are updated by control variables, used in the model. There are no restrictions on circuit topology and switch connections. The switches can be both externally and internally controlled. The inconsistent initial value problem and Dirac delta impulses occurring because of ideal switch are discussed in detail. Two examples are given concerning the analysis of circuits with ideal switch.

A parallel L_βC_α tank circuit with an α-order capacitor and a β-order inductor is proposed in this paper, where α and β are positive real numbers. The impedance of the parallel L_βC_α tank circuit, which could perform as a pure real, pure imaginary or short impedance, is discussed in detail, followed by the phase response analysis in α – β plane. The results show that the parallel L_βC_α tank circuit could act as a constant phase element. The resonance frequency analysis demonstrates that there exists more than one resonance frequency. And the time domain response expression of the proposed L_βC_α tank circuit is given by applying the inverse Laplace transform. The dual transformation relationship between the series and parallel L_βC_α tank circuit is summarized at last.

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

Hash functions are among the crucial modules of modern hardware cryptographic systems. These systems frequently operate in harsh and noisy environments where permanent and/or transient faults are often causing erroneous authentication results and collapsing of the whole authentication procedure. Hence, their on-time detection is an urgent feature. In this paper, a systematic development flow towards totally self-checking (TSC) architectures of the most widely-used cryptographic hash families, SHA-1 and SHA-2, is proposed. Novel methods and techniques are introduced to determine the appropriate concurrent error detection scheme at high level avoiding gate-level implementations and comparisons. The resulted TSC architectures achieve 100% fault detection of odd erroneous bits, while, depending on the designer's choice, even number of erroneous bits can also be detected. Two representative functions of the above families, namely the SHA-1 and SHA-256, are used as case studies. For each of them, two TSC architectures (one un-optimized and one optimized for throughput) were developed via the proposed flow and implemented in TSMC 0.18 μm CMOS technology. The produced architectures are more efficient in terms of throughput/area than the corresponding duplicated-with-checking ones by 19.5% and 23.8% regarding the un-optimized TSC SHA-1 and SHA-256 and by 20.2% and 24.6% regarding the optimized ones.

Biometrics-based authentication is an effective approach which is used for automatically recognizing a person's identity. Recently, it has been found that the finger-knuckle-print (FKP), which refers to the texture pattern produced by the finger knuckle bending, is highly unique and can be used as a biometric identifier. In this paper, we present an effective FKP recognition scheme for personal identification and identity verification. This method is a new encoding scheme based on local binary pattern (LBP). Each image first is decomposed in several blocks, each block is convolved with a bank of Gabor filters and then, the LBPs histograms are extracted from the convolved images. Finally, a BioHashing approach is applied on the obtained fixed-length feature vectors. Extensive experiments conducted over the Poly-U FKP database demonstrated the efficiency and effectiveness of our proposed method.