Journal of Circuits, Systems and Computers

This work presents a novel security platform for industrial communications using a nine-MicroBlaze MPSoC. This platform has low power consumption and cost, therefore, it is very appropriate for embedded systems, where restrictions on cost and power consumption have to be fulfilled. This system uses the RSA asymmetric algorithm combined with the AES symmetric algorithm, which was developed using two encryption modes, ECB and CBC. In this way, the platform makes possible to combine different algorithms and modes in function of the necessities of speed and security required. Furthermore, due to the implementation of standard algorithms (AES and RSA) and modes (ECB and CBC), this platform can be connected to the Internet, and can even use secure protocols as SSL.

Frequency-dependent image interference is an inevitable impairment in wideband quadrature receivers. To suppress this interference, this paper presents a non-data-aided adaptive compensation algorithm, optimal block adaptive filtering algorithm based on circularity (OBA-C). This technique exploits the concept that the image interference in wireless systems causes the received complex signal to lose its nature of circularity. Then the OBA-C algorithm restores the circularity of the signal to compensate for the image interference. To avoid manually selecting a step size, the presented algorithm employs the complex Taylor series expansion to optimally update the adaptive filter coefficients. This technique fully exploits the degrees of freedom of the system, and generates an individual update for each filter coefficient at each iteration. Computer simulations are carried out to test the performance of the OBA-C for practical levels of image interference. The simulation results illustrate that the OBA-C achieves fast convergence and excellent image rejection performance. Other advantages of OBA-C are also analyzed, including the robustness against radio frequency impairments and different levels of image interference.

For an active multi-port network of a direct current, as a model of a power supply system, the problem of recalculation of the changeable loads currents is considered. The approach on the basis of projective geometry is used for interpretation of changes or "kinematics" of regime parameters of a circuit. The changes of the regime parameters are introduced otherwise, through the cross ratio of four points with use of projective coordinates. Easy-to-use formulas of the recalculation of the currents, which possess the group properties at change of conductivity of the loads, are obtained. It allows expressing the final values of the currents through the intermediate changes of the currents and conductivities. Disadvantages of the traditional approach, which uses the changes of resistance in the form of increments, are shown. The given approach is applicable to the analysis of "flowed" form processes of the various physical natures.

In this paper, several hardware architectures for the realization of ensembles of axis-parallel, oblique and nonlinear decision trees (DTs) are presented. Hardware architectures for the implementation of a number of ensemble combination rules are also presented. These architectures are universal and can be used to combine predictions from any type of classifiers, such as decision trees, artificial neural networks (ANNs) and support vector machines (SVMs). Proposed architectures are suitable for the implementation using Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Experiment results obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in the classification time in comparison with the traditional software implementations. Greatest improvement can be achieved using the SP2-P architecture implemented on the FPGA achieving 416.53 times faster classification speed on average, compared with the software implementation. This result has been achieved on the FPGA working at 135.51 MHz on average, which is 33.21 times slower than the operating frequency of the general purpose computer on which the software implementation has been executed.

The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.

Modern field programmable gate arrays (FPGAs) offer built in support for efficient implementation of signal processing algorithms in the form of specialized embedded blocks such as high speed carry chains, specialized shift registers, adders, multiply accumulators (MAC) and block memories. These dedicated elements provide increased computational power and are used for efficient implementation of computationally extensive algorithms. This paper proposes a novel algorithm and architecture for the design and implementation of high performance intermediate frequency (IF) filters on FPGAs. In this research, we have proposed innovative design methodologies for generation of optimal feed forward and recursive architectures to be mapped on a family of FPGAs. Keeping in perspective the limited number of registers within the embedded blocks, the new methodology applies transformations to achieve higher throughput by applying various optimizations to the design algorithm. Implementation options include systolic MAC, transpose direct form MAC, canonic signed digit and distributed arithmetic based filters to suite the most economical FPGA implementation. The paper demonstrates the methodology and shows its applicability by synthesizing the designs and comparing the results to a number of traditional architectures and intellectual property cores. Using Xilinx Virtex-5 FPGA, our results show a throughput improvement between 7% and 30% with an average improvement of 16% over traditional implementations of these designs.

In this paper, subharmonic and chaotic behavior in current controlled DC drive has been investigated. The effects of variation of some chosen parameters on the qualitative behavior of the system have been studied. To avoid occurrence of chaos we present a method for controlling chaos applicable to DC drives. The results of numerical investigation are presented.

Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market.

This work analyzes a JPEG encoding algorithm mapped onto a configurable M × N, mesh/torus, NoC platform described in SystemC with the transaction level modeling (TLM) standard; timing constraints for both, the router and network interface controller, are assigned according to a hardware description language (HDL) model written for this purpose. Processing nodes are also described as SystemC threads and their computation delays are assigned depending on the amount and cost of the operations they perform. The programming model employed is message passing.

We start by describing and profiling the JPEG algorithm as a task graph; then, four partitioning proposals are mapped onto three NoCs of different size. Our analysis comprises changes in topology, virtual channel depth, routing algorithms, network speed and task-node assignments. Through several high-level simulations we evaluate the impact of each parameter and we show that, for the proposed model, most improvements come from the algorithm partitioning.

In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic more energy efficient than conventional CMOS logic.

Due to its low leakage power and high density, spin torque transfer RAM (STT-RAM) has become a good candidate for future on-chip cache. However, STT-RAM suffers from higher write energy compared to the SRAM. One state-of-the-art technique to alleviate this problem is read-before-write (RBW). In this paper, we study the pattern of the write accesses to the L2 cache and show that directly applying the RBW to a STT-RAM L2 cache can be problematic from energy perspective. We then propose a selective read-before-write (SRW) scheme to further reduce the dynamic write energy of the STT-RAM cache. Additional optimizations are included in the design of SRW so that it can save a considerable amount of energy at negligible overheads. The experimental results show that SRW achieves a 86.0% reduction in write energy consumption vs. a baseline without any write optimization techniques, and a 6.55% more reduction compared to the RBW scheme.