Journal of Circuits, Systems and Computers

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.

Dynamic Partially Reconfiguration (DPR) designs provide additional benefits compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design flow, designers have to manually define the dimensions and positions of Partially Reconfigurable Regions (PR Regions). The following fine-grained placement for system modules is also limited because it takes the floorplanning result as a rigid region constraint. Therefore, the manual floorplanning is laborious and may lead to inferior fine-grained placement results. In this paper, we propose to integrate PR Region floorplanning with fine-grained placement to achieve the global optimization of the whole DPR system. Effective strategies for tuning PR Region floorplanning and apposite analytical evaluation models are customized for DPR designs to handle the co-optimization for both PR Regions and static region. Not only practical reconfiguration cost and specific reconfiguration constraints for DPR system are considered, but also the congestion estimation can be relaxed by our approach. Especially, we established a two-stage stochastic optimization framework which handles different objectives in different optimization stages so that automated floorplanning and global optimization can be achieved in reasonable time. Experimental results demonstrate that due to the flexibility benefit from the unification of PR Region floorplanning and fine-grained placement, our approach can improve 20.9% on critical path delay, 24% on reconfiguration delay, 12% on congestion, and 8.7% on wire length compared to current DPR design method.

Chemical-mechanical polishing (CMP) is an essential process in deep-submicrometer LSI manufacturing to achieve Chip's planarization. It includes two processes: back-end-of-line (BEOL) and front-end-of-line (FEOL). This paper focuses on the problem of BEOL in 65 nm copper process. Although model-based dummy metal fill has become a tendency recently, the proposed improved rule-based dummy fill is appropriate still. A middle scale design is used for simulation. The metal density, oxide thickness, copper thickness, capacitance variation and variation of layout data size were investigated. The results show that improved rule-based dummy fill and model-based dummy fill have the same planarization, and proposed method has small capacitance variation. The GDS file size of the proposed rule-based fill is less than the model-based fill's.

Nowadays, many simulations, implementations, synchronization and secure communication applications of chaotic circuits have been introduced in literature. However, electronics circuit design and implementation of nonlinear Sprott Case H chaotic system and its synchronization were not found in the literature. In this paper, numerical model, electronics circuit simulation and implementation electronics circuits of the Sprott Case H chaotic system and its synchronization by the method of Pecora and Carroll (P–C) complete replacement (CR) were performed. The simulation and implementation results showed that the Sprott Case H chaotic system can be synchronized and thus can be used for secure communication and encryption applications.

This paper presents an innovative driver circuit for a new current regulator of the multilevel inverters. The proposed regulator has a PI controller to guarantee the optimum tracking for the reference current. This proposed regulator has the advantage of integration between the PI controller and the multicarrier switching operation. This regulator fits the operation of multilevel and cascaded converters. The suggested current regulator is compared with several existing current regulators of the multilevel and cascaded converters. The performance of the proposed regulator is verified using simulation results in comparison with the performance of the common existing current regulators for the multilevel inverter. Moreover, this paper shows the performance of the new regulator in power system applications.

A comprehensive analysis of the impact of the finite gain-bandwidth product (GBW) in amplifiers and the excess loop delay on a parallel multibit CT ΔΣ ADC for an orthogonal frequency division multiplexing OFDM ultra-wideband (UWB) receiver has been carried out in this paper. The overall converter consists of two CT ΔΣ modulators covering two sub-bands (each of them implemented by a third and a fourth order CT ΔΣ modulator) that are arranged to operate in parallel. Our study was based on the dependence of the noise transfer function (NTF) poles and zeroes locus in the z-plane on these two nonideal effects for both modulators from a theoretical approach. The corresponding STFs were also analytically evaluated. System-level simulations have been accomplished too. Amplifiers were modeled according to a single-pole transfer function. Using the modified Z-transform method the dependence of the NTF poles and zeroes locus in the z-plane on the finite GBW and on excess loop delay was obtained when the DAC pulse end occurs in the current ("early") or in the following ("late") clock cycle. NTF poles and zeroes loci were evaluated as a function of the two nonideal effects considered separately or combined.

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

Based on TSMC 0.18 μm 1.8 V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0 V supply and 200 KS/s, the ADC achieves an signal-to-noise and distortion-ration (SNDR) of 59.78 dB and consumes 3.03 μW, resulting in a figure-of-merit (FOM) of 19.0 fJ/conversion-step. The ADC core occupies an active area of only 260 × 220 μm².

This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward ΣΔ modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted summation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asynchronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power consumption. A 0.13-μm CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 μW from a 0.8 V supply at an 800-kHz sampling rate.

This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications — here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.