Journal of Circuits, Systems and Computers

Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

According to the terminal relations of the DO-OTA, eight nullor–mirror models for the DO-OTA are presented in this paper, Moreover, the NAME method for two different classes of T-T filters is considered. The class I filters, employing three SISO-OTAs, have 16 different forms, and the class II filters, employing one SISO-OTA and one DISO-OTA or one SIDO-OTA, have eight different forms. Due to use of canonic number of components, the circuits are easy to be integrated and their parameters can be tuned electronically through tuning bias currents of the OTAs. The MULTISIM simulation results have been included to verify the workability of the derived circuit.

This paper proposes an isolated multi transformer cell inverter employing several transformer cells. Some of the cells contain two unidirectional switches that generate two voltage levels and only last cell has five switches that provide five voltage levels. The proposed inverter configuration reduces a number of switches compared with both traditional cascaded transformer multilevel inverter and other multi transformer inverters including six switches in last cell. Also, a prototype has been implemented using DSP-based processor provides a high number of output levels in symmetric and asymmetric states. The operation and performance of the suggested inverter has been proved by simulation result and experimental results.

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 μW at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-μm 3.3 V BiCMOS technology.

New FPGA families can be reconfigured partially, meaning that only a certain portion of the chip area is reprogrammed. Partial reconfiguration makes possible to exchange function blocks on the FPGA and adapt it to a changing environment. It is used to have only a subset of necessary applications running on chip at each time, and replacing them by those needed. One of the challenging problems is the scheduling and the placement of modules on reconfigurable resources, this problem is called temporal placement. Several modules placement techniques have been introduced in the literature to solve the temporal placement problem. In this paper, we examine the temporal placement, showing how it can be decomposed into a number of distinct but not independent subtasks. Furthermore, in this paper, we have classified the temporal placement algorithms into the following classes:

(1) Algorithms without design optimization

(2) Routing cost optimization algorithms

(3) Reconfiguration time optimization algorithms

(4) Modules interfering optimization algorithms

(5) Device resources optimization algorithms

After that, experiments are conducted in order to evaluate the complexity and performances in term of traditional design metrics, like latency, area, etc., of each algorithm.

The methods are proposed targeting to reduce the numbers of both look-up table elements and embedded memory blocks in the logic circuit of a Moore finite state machine. The proposed methods are based on binary encoding of both classes of pseudoequivalent states and collections of microoperations. Examples of synthesis and results of investigations are given.

In this paper, a novel first-order current-mode (CM) electronically tunable all-pass filter including one grounded capacitor and two dual-output current followers (DO-CFs) is presented. The used DO-CFs are implemented using only 10 MOS transistors granting the proposed CM all-pass filter extremely simple structure. The proposed filter is suitable for integrated circuit (IC) fabrication because it employs only a grounded capacitor and is free from passive component matching conditions. Interestingly the introduced configuration uses minimum number of components compared to other works. It also offers other interesting advantages such as, alleviating all disadvantages associated with the use of resistors, easy cascadability and satisfies all technology requirements such as small sizing, simple realization, low voltage and low power operation. Additionally, the circuit parameters can be easily set by adjusting control voltages. Most favorably, the proposed CM all-pass filter can be simply used as a voltage-mode (VM) all-pass filter with outstanding properties of adjustable gain and tunability. To further show the versatility of the proposed structure a sinusoidal oscillator is also derived from presented CM all-pass filter. Nonideal gain and parasitic impedance effects on developed CM filter are discussed. Finally, simulation results with SPICE program are included to confirm the theory.

One approach to design self-tuning g_m-C biquad band-pass filter is considered in this paper. The phase control loop is introduced to force filter central frequency to be equal to input signal frequency what is achieved by adjusting the amplifier transconductance g_m. Thanks to that, the filter is robust to parameter perturbations and it can be used as a selective amplifier. In the full tuning range, it has a constant maximum gain at central frequency as well as a constant bandwidth. The 0.25 μm SiGe BiCMOS technology was used during design and verification of the band-pass filter. The filter has 26 dB gain, quality factor Q = 20 and central frequency up to 150 MHz. Simulation results indicate that the total in-band noise is 59 μV_rms, the output third intercept point OIP3 = 4.36 dB and the dynamic range is 35 dB. Maximal power consumption at 3 V power supply is 1.115 mW.

In this paper, predictive control has been implemented by several methods in a most simplified manner for quadruple tank system, i.e., a multi-input multi-output control problem. Quadruple tank system is a nonlinear system which can be adjusted to obtain two different class of system i.e., minimum and nonminimum phase, therefore tuning for each phase of system has to be tackled separately. Control system design has been obtained by manual proportional-integral controller, traditional generalized predictive control, predictive proportional-integral-derivative on the basis of generalized predictive control, predictive iterative learning control and finally adaptive predictive proportional-integral-derivative control has been developed successfully. Stability and performance of the each control system design has also been discussed.

In this paper, an algorithm for smoke region of focus (ROF) detection based on surveillance video is proposed in order to solve the problem of limited application in scenes range and imaging environment of the traditional smoke detection algorithm. The frog vision perception model is used in this algorithm. First the suspect regions are detected, and then the static and the dynamic features of the regions are chosen for the smoke ROF detection. Experimental results show that the algorithm is efficient and significant for improving the operational rate of the detection.

In this paper, a multiband low-noise amplifier (LNA) with capability of band tuning is proposed to support the Mobile WiMAX (IEEE 802.16e) standard associated with a large IIP3 at RF frequencies using multi-gated linearization techniques. Proposed LNA architecture has been optimized in terms of linearity based on a comparative analysis between four tunable LNA structures. In addition, a general survey is performed on linearization techniques (multiple-gated transistors, Derivative Superposition (DS), Modified DS). Proposed LNA is constituted of multi-gated linearization technique. Design and simulations have been realized in 0.13 μm RF CMOS process considering a power supply of 1.2 V. Proposed LNA exhibits an IIP3 of +8.8 dBm, +14.3 dBm, and +6.4 dBm at the lower, middle, and upper bands of WIMAX, respectively. It results in a power gain of 10 dB, a noise figure below 2.5 dB and S₁₁ of -11.5 dB, -8.6 dB, and -12.7 dB at the lower, middle, and upper bands. The related power dissipations are 10 mW, 9.9 mW, and 9.4 mW at the lower, middle, and upper bands, respectively.

We present a study of the effects of active queue management (AQM) on the average queue size in routers. In this work, three prominent AQM schemes are considered: packet classification, checking service level agreements (SLA) and queue scheduling. This paper presents several adaptive resource sharing models that use a revenue criterion to allocate bandwidth in an optimal way. The models ensure QoS requirements of data flows and, at the same time, maximize the total revenue by adjusting parameters of the underlying schedulers. Deficit round robin (DRR) and deficit weighted round robin (DWRR) scheduling techniques have shown their ability in providing fair and weighted sharing of network resources for network devices. However, they are unable to use the total allocated network bandwidth even in burst traffic. In this paper, we propose a negative-deficit weighted round robin (N-DWRR) technique as a new packet scheduling discipline to improve the bandwidth utilization rate without increasing the total latency. A fully hardware packet scheduler has been implemented and verified as part of an intellectual property core. This is motivated by the fact that the design and analysis of hardware/software architectures for such techniques requires new models and methods, which do not fall under the domain of traditional embedded-systems design.

The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously. However, the design is not as intuitive as one might at first think. In this paper, we present a detailed analysis of the single cascode amplifiers. The relationship between gain and bandwidth is important. When used to achieve maximum bandwidth the voltage gain of the common-source stage is close to unity. However, when the cascode is designed to obtain a high voltage gain, then the gain-bandwidth trade-off, typical in the common source amplifier, reappears. This analysis is used to provide the basis for practical cascode amplifier design.

In this letter, a tunable high-Q active inductor with high dynamic range is presented. The equivalent inductance and resistance values can be tunable in a wide frequency range by changing the compensating network components values; outside the operating frequency band, the equivalent resistance increases, improving signal rejection for band-pass filter applications. A second-order active band-pass filter with a central frequency of 2100 MHz using the high-Q active inductance has been fabricated and tested.

In this work, a wideband and high-performance CMOS implementation of 2nd-generation current conveyor (CCII) is proposed. The proposed circuit is composed of a high performance voltage follower stage which is based on differential pairs to provide high voltage swings on input and output ports and a current follower stage. It is shown that the proposed voltage follower stage can be used to implement high performance 1st and 3rd-generation current conveyors (CCI and CCIII, respectively) that have very small equivalent impedances on ports X, high equivalent impedances on ports Y and Z and also high-valued voltage and current transfer bandwidths. 2nd and 3rd order filter circuits as well as a half-wave rectifier circuit are given to show the performance and usefulness of the proposed current conveyor circuits. The simulation and experimental results are given to verify the theoretical analyses.