Journal of Circuits, Systems and Computers

In this paper, an efficient method for designing memoryless modulo {2ⁿ ± k} multipliers is proposed, which can be used to compose larger residue number system (RNS) moduli sets. This technique includes a novel choice for the weights associated with the partial products of the inputs is used, which improves the performance of the resulting multipliers. Experimental results suggest that the use of this choice of input weights in the structure herein proposed, provides an average improvement of 36.3% in area-delay-product (ADP) in comparison with the related state-of-the-art. Furthermore, the structures presented in the state-of-the-art are also improved by 43.5% in ADP.

High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm² area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.

This paper represents a new enhanced Colpitts oscillator, which is designed based on g_m-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, the differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using 0.18 μm technology and is simulated under 1.8 V supply voltage in advanced design system (ADS). Simulations show the output phase noise of -140 dBc/Hz at 1 MHz offset frequency when the operating frequency is 1 GHz.

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

In the design of high performance complex arithmetic logic circuits, ground bounce noise, leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, the low power and reduced ground bounce noise using 10 transistor full adder has been proposed. Full adder is the most important basic building of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also for address generation in processors and microcontrollers. It is therefore necessary to make these systems more efficient so that they consume less power. Here, we use stacking power gating technique to evaluate leakage current, power and ground bounce noise. This paper describes reduction of leakage power and ground bounce noise from the 10 T full adder circuits to make it more reliable to be used to have low power and stable and errorless output. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltages and various temperatures. By using this technique the leakage current reduction can be improved by 80% and leakage power to 70% as compared to conventional 10 T full adder. Ground bounce noise can be reduced to 60% as compared to the base full adder.

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

Analysis of the noise voltage density evaluation procedures of the ultrasonic preamplifier is presented. Ultrasonic testing is demanding low noise reception channel. Techniques and equipment for ultrasonic preamplifier's noise performance evaluation are suggested. Equipment used and measurement technologies applied are described. One of the techniques suggested allows estimating the preamplifier noise with only impedance measurement results available. Sine wave correlation technique was used in the impedance measurement procedure. Another technique, not demanding the spectrum analyzer, was suggested, which uses the analog-to-digital converter (ADC) sampling and the Fourier transform to obtain the noise spectral density. Experimental results for the measured complex gain and the equivalent input noise of the preamplifier are presented. Comparison with traditional noise estimation procedure, using the spectrum analyzer is given. Both direct measurement techniques (ADC record Fourier analysis based and spectrum analyzer) indicated good match. Noise whiteness was estimated: in a region of operation frequencies, 5–7 MHz, noise can be considered as white.

Phase-locked loops (PLL) is a phase and/or frequency tracking system, widely used in communication and control systems. The sinusoidal multiplicative type PLL still remains a recurrent model, due the fact that its derivation is originated from the maximum likelihood approach. In this note, it is showed as a generalized product, called q-product, which can be used to implement the phase detector and improve some important parameters of the PLL system, as the block linearity and pull-in characteristics. Numerical examples are presented in order to illustrate the proposal.

The similarity between unloaded synchronous motor (SM) pull-into-step mechanism and phase locked loop (PLL) synchronization procedure is revealed in this letter. It is shown that both processes possess analogous structure and may therefore be described by same type of equations. As a result, the methodologies used for describing the phase locked loop synchronization may be useful in synchronous motor starting process analysis and vice versa.

Arithmetic circuits in general do not exactly match specifications, leading to different implementations within allowed imprecision. Starting from real-valued representation, such as Taylor series, we propose a new technique based on arithmetic transform (AT) to analyze simultaneous selection of multiple word lengths and even the function approximation schemes, and then derive a verification algorithm to check whether an implementation fits the error bound. To find optimized implementations which both satisfy a given error bound and constraints included interface input, delay and area. An optimization algorithm is derived to explore multiple precision parameters and get the optimized implementations by various constraints.

In this paper, an optimized design procedure based on genetic algorithm (GA) for automatic synthesis of dual-band concurrent fully integrated low-noise amplifiers (LNA) targeted to 802.16d @ 3.5 GHz and 802.11b, g @ 2.4 GHz standards is discussed. The algorithm delivers the circuit elements geometry, rather than their values, and bias levels to secure the best level of LNA gain, input matching, output matching and power consumption. Working on the components geometry level aims at considering the elements parasitic effects. The basic cascode and a current reuse folded cascode LNA's are tried. GA as an optimization engine is programmed in MATLAB and performance evaluation in 0.18 μm RF CMOS TSMC technology is ceded to HSPICE. Results indicate that the automated scheme well computes the desired circuit in an acceptable time span; otherwise, it may be explored by either tremendous manual trial and error or astronomical cycles of an exhaustive search. This is not accomplished without imposing certain approximate search space constraints.

High-radix router based on the tile structure requires large amount of buffer resources. To reduce the buffer space requirement without degrading the throughput of the router, shared buffer management schemes like dynamically allocated multi-queue (DAMQ) can be used by improving the buffer utilization. Unfortunately, it is commonly regarded that DAMQ is slow in write and read. To address this issue, we propose a fast and fair DAMQ structure called F2DAMQ for high-radix routers in this paper. It uses a fast FIFO structure in the implementation of idle address list as well as data buffer and achieves some critical performance improvement such as continuous and concurrent write and read with zero-delay. Besides, F2DAMQ also uses a novel credit management mechanism which is efficient in avoiding one virtual channel (VC) monopolizing the shared part of the buffer and achieving fairness among competing VCs sharing the buffer. The analyses and simulations show that F2DAMQ performs well in achieving low latency, high throughput and good fairness under different traffic patterns.

In this paper, we propose a tunable CRLH ZOR based on the latest resurgent of ferroelectric materials. It is known that for most resonant structures, attainment of optimal performance requires some level of additional tuning through either mechanical means (i.e., with tuning screws) or other coupling mechanisms. Therefore, incorporation of electronic tuning into high temperature superconductor (HTS) material components without degradation of performance is very attractive. The result will be low-loss microwave components that could be fine-tuned for optimal performance, with the additional attribute of being tunable over a broadband frequency range. The dielectric properties of the ferroelectric thin film, and the thickness of the ferroelectric film, play a fundamental role in the frequency or phase tunability and the overall insertion loss of the circuit. The main driving force toward using the ferroelectric is the potential for substantial miniaturization of microwave components and systems and the potential for integration with microelectronic circuits due to the development of thin and thick film ferroelectric technology. The ZOR is designed, and simulated by the full-wave analysis software. The response shows a variation of electromagnetic characteristics with the applied electric field, ferroelectric thickness and the operating temperature.

The theoretical and numerical analysis proposed in this paper is totally original and the essential purpose is to introduce an innovative procedure to represent some of the more important digital communications signals by using a simple mathematical tool. All new analytical concepts presented here can be used as definitions of these signals and the great improvement is the fact that we can manipulate all of them through some flexible as well as original mathematical operations. This theoretical technique permits us to represent all classic analogical waves by using periodic and non-periodic continuous functions such that they can be seen as a video color signal or a simple sequence of zeros and ones. By using a nonlinear operator, it is possible to define analytically a wide class of important electromagnetic waves.

Two parallel algorithms are proposed in this paper for solving the problem of finding exact exclusive-or sum of products (ESOP) expressions for an arbitrary Boolean function. This minimization problem is a very difficult one and solutions have been proposed only for up to seven variables. The processing time for some symmetric functions of seven variables is of the order of weeks. The proposed algorithm is a hybrid one (OpenMP, MPI) and a speed-up of more than nine could be achieved, for a cluster of three nodes with four cores each.