Journal of Circuits, Systems and Computers

A critical evaluation of high-power electronics switching in semiconductor materials is made from the standpoint of performance, reliability, and commercial viability. This study takes into account recent experimental results obtained from the field-reliability study of silicon power MOSFETs in high-density power supplies where residual material defects present in the space charge region of the device were found to generate local micro plasma that eventually caused power MOSFETs to fail. Based on these results and commercial progress made to date in wide bandgap semiconductor technologies, it is suggested that silicon carbide (SiC) promises to be the preferred material for high-power electronics switching from cost, performance and reliability considerations — this assessment is further strengthened by the near-term potential for developing large-area, low-cost, and defect-free SiC bulk substrates and epitaxial layers. This conclusion is also supported by the feasibility and the need for vertical, MOS-controlled, bipolar power switches in compact and efficient megaWatt-level power converters in order to make transformational changes in the 21st century electrical transmission and distribution infrastructure.

In this work, TaN bottom electrode thermal sensing resistor for MEMs-based bolometer was designed and fabricated by 200 mm Cu-BEOL compatible process. Thermal sensing material was B-doped alpha-Si deposited by PECVD in situ doping process. PVD TaN film was used as the bottom electrode. Dedicated process on modified tool was introduced to achieve a good contact between the TaN and the sensing material. There are both CVD and Etch chambers installed on this modified tool. Wafer with bottom electrode pattern was pre-cleaned firstly by low-power Ar/CF4 gas to remove oxide and possible surface residue on TaN in the etch chamber. Then, the wafer was transferred to CVD chamber through transfer chamber in vacuum condition. With vacuum transfer condition under tight Q-time control, Ohmic contact can be achieved for the TaN bottom electrode and B-doped alpha-Si. Through the IV curve and TCR data, it can be seen that the bottom electrode device can well meet the MEMs-based bolometer requirements.

On-chip stacked-spiral radio-frequency (RF) inductor with vertical nanopowder-magnetic-core was proposed and implemented in standard 0.18 μm six-metal CMOS with a post-CMOS backend process module (i.e., CMOS+). To improve on the prior open-magnetic-circuit-loop structure and thus limited improvement at multi-GHz performance, the non-traditional concept shows vertical magnetic core forming a near closed magnetic loop. The ferrite nanoparticle-magnetic-core reduced magnetic loss to improve L-density to 9 GHz. Results show the proof-of-concept designs greatly increase the inductance, L, by up to 34% and the factor, Q, by 62% over a multi-GHz frequency range.

Gate-All-Around (GAA) MOSFETs have been investigated as promising new device structures, and Germanium is used for its high carrier mobility. In this paper, a 3D parallel Monte Carlo simulation of GAA Ge nanowire nMOSFET with effective potential method is implemented. Compared the simulation results with classical results, we can see that the quantum effects affect on the distribution of density, velocity and energy, and they make a decrease on the drain current as well.

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

The performances of proton irradiated silicon–germanium (SiGe) power heterojunction bipolar transistors (HBTs) at extreme temperatures (liquid nitrogen temperature and high stage-temperature of 120°C with junction temperature over 160°C) are reported in this work. SiGe power HBTs with total emitter area of ~ 1460 μm² are fabricated in a commercial BiCMOS process, and irradiated with proton at different fluences from 1 × 10¹² p/cm² to 5 × 10¹³ p/cm². Experimental characterizations are conducted for pre- and post-radiation devices at room temperature, cryogenic temperature and high temperature. The results demonstrate that the proton-irradiated SiGe power HBTs are naturally suitable for electronic operations at extreme temperatures. Specifically, investigation of proton radiation on SiGe power HBTs at liquid nitrogen temperature (77 K) indicates a significant potential for space applications. In addition, SiGe power HBTs show better tolerance of proton radiation at high temperature of 120°C (junction temperature over 160°C). SiGe power HBTs demonstrate great potential in power amplification for wireless communication systems under severe radiation and extreme temperature environment (cryogenic and high temperatures) even without any intentional radiation hardening.

Ultra-wide band (UWB) microwave imaging is a promising method for the breast cancer detection based on the large contrast of electric parameters between the malignant tumor and its surrounded normal organisms. In this paper, a two-dimensional model of the breast organisms is numerically carried by the finite difference time domain (FDTD) method. The dispersion characteristics of the breast media are taken into account by single pole Debye model to approach the actual properties of the breast organism. In this method, a tumor is assumed in the model with two cases. The standard Capon beamforming (SCB) and doubly constrained robust Capon beamforming (DCRCB) algorithm performed to reconstruct the image is described in detail. The tumor can be detected and localized using the proposed algorithm and the result demonstrates a good stability of DCRCB algorithm.

A low dropout (LDO) linear regulator with pre-regulator is presented in this paper. The LDO is suitable for wide power supply of 4.5–28 V for smart battery system applications to generate a stable 1.8 V output. The proposed LDO provides high stability by pre-regulator for a rough 3.3 V as internal power supply and multi-zero and multi-pole frequency compensation. The scheme of combining of using output capacitor to set a dominant pole, utilizing a buffer stage to avoid generation of low-frequency pole, introducing an additional zero, is presented to stabilize the regulator loop for various load conditions and wide supply range. Besides, parasitic poles in high frequency can be compensated by feed-forward compensation and mirror-pole compensation.

A novel silicon-on-insulator (SOI) high voltage device with a composite dielectric buried layer (CD SOI) is proposed in this paper. In the proposed structure, the composite dielectric buried layer consists of Si₃N₄ dielectric and low-k (relative permittivity) dielectric. The electric field strength in the buried layer is enhanced by the low-k dielectric. The Si₃N₄ dielectric in the buried layer not only modulates the electric field distribution in the drift region, but also provides a heat conduction path for the SOI layer and alleviates the self-heating effect (SHE). The breakdown voltage (BV) = 362 V for CD SOI is obtained by simulation on a 1 μm SOI layer over 2 μm buried layer, which is enhanced by 26% compared with that of conventional SOI.

The noise of the current accumulator is analyzed. A model of time-delay-integration (TDI) CMOS image sensor is presented, which is used to analyze the noise performance. In this model, input signals are accumulated four times by the type of current and then converted to digital signals to accomplish the other accumulation by 32 times, i.e., 4 × 32 accumulation mode. The noise, which includes switch charge injection, sample noise and kT/C noise, is considered in this model. The major source of the noise and the relationship between noise and sample capacitance are evaluated through the model simulation. The results indicate that the total noise can be restrained by increasing sample capacitance. When the input signal is arranging from 0 μA to 100 μA, the accuracy of the current accumulator can be 11 bits by using 1 pF sample capacitor. The SNR of the output signal can be increased by 20.38 dB which is close to the ideal result. The circuit of the current accumulator based on the model is also proposed.

In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems.

In this paper, a capacitive interface circuit with capacitor mismatch auto-compensation has been designed and implemented for MEMS gyroscope. An on-chip capacitor array controlled by an 8-bit SAR logic circuit is selected to be connected in parallel with the minor one of the two differential gyroscope capacitors, making the two capacitors equal. The compensation progress takes eight periods of the clock at power-on and then will be turned off automatically. The chip is fabricated in a 0.35 μm CMOS process. The test of the chip is performed with a vibratory gyroscope on the condition of a closed-loop control in the drive mode, and the measurement shows that the minimum capacitive compensation is 3.5 fF. Within -300°/s to 300°/s of rotation rate input range, the nonlinearity is less than 0.1%.

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm². By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm².

This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz–50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm² × 0.3 mm² using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply.

A fully integrated push–push voltage controlled oscillator (VCO) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 μm SiGe BiCMOS technology is presented. Multi-coupled LC tanks are used to improve the tuning range, power consumption and phase noise. Digital tuning varactors are used to maintain a low VCO tuning sensitivity (K_VCO) and maximum frequency overlap. The VCO achieves a frequency tuning range (FTR) of 17% at 12 GHz, a phase noise of -106.62 dBc/Hz at 1 MHz offset and consumes 7 mW from 1.8 V supply.

By analyzing the operation characteristic of linear feedback shifter registers (LFSRs) in many public stream cipher algorithms and its bottleneck realized by general processor, each specific instruction and reconfigurable hardware cell are proposed in this paper, which can neatly execute LFSR computing operation in parallel with high performance. The LFSR instructions can sustain different operation data widths, different operating models. Instruction-level parallelism based on VLIW system structure and instruction inner parallelism by operating several steps at one time are exploited too. Corresponding reconfigurable hardware units to sustain the implementation of each instruction forcefully by configurating is also developed. The circuit can be used as an important accelerated unit in special processing for stream cipher.

Reed–Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision (ASD) decoding of RS codes can obtain significant coding gain over hard-decision decoding. Compared with other ASD algorithms, the low-complexity chase (LCC) decoding algorithm needs less computation complexity with similar or better coding gain. To reduce the latency of the interpolation, multiple interpolators can be applied. However, the interpolator has to finish the forward interpolation (FI) which costs more iterations before it turns to the unified-backward–forward interpolator (UBFI). In this paper, FI and UBFI are carried out by two different interpolators. A novel pipelined interpolator (NPI) architecture is proposed which includes a parallel forward interpolator (PFI) and a reduced-complexity multi-interpolator (RCMI). For the (255, 239) RS code with η = 5, the interpolation latency and the efficiency will be 44% and 1.76 times of the previous design, respectively.

This paper presents a formal and model driven design approach for a high speed data transmission channel. The formal process algebra communicating sequential processes (CSP) was used to specify the system functionality. Automated model checking established, beyond reasonable doubt, important system properties, such as freedom from deadlock and livelock. Once these properties were established, the functionality was translated into an implementation which realizes high speed data transmission between two independent IC chips. Normal and failure case testing ensured that the implementation complies with the specification. This work shows how formal and model driven design methodologies speed up the process of turning ideas into physical problem solutions. More specifically, formal modeling gave us firm understanding and deep insight of the system functionality which enabled us to implement and to select correct system components.