Journal of Circuits, Systems and Computers

In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of DCOs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of DCOs and the possible tendency for future work in summary.

This paper addresses the optimization problem on subcarrier and power allocation of orthogonal frequency division multiple access (OFDMA) system under spectral efficiency (SE) metric when deploying superposition coding (SC) transmission strategy. An algorithm with polynomial time complexity, of the order of (UNlog₂(N)) has been proposed for sub-optimal SE maximization. Results indicate that the system SE increases with the use of SC technique. Besides, the throughput gain with SC adoption increases when the number of users (U) approaches the number of subcarriers (N) available in the system.

Comparison of two high power pulser topologies is presented. Pulser design was aimed for piezoelectric transducer excitation, yet it can also be used for electromagnetic acoustic transducer (EMAT) or capacitive micromachined ultrasonic transducers (CMUTs) excitation. Pulser can produce both single rectangular pulse and trains of rectangular arbitrary duration pulses. In order to achieve the economy of the electrical power consumption and speed both high-pulling and low-pulling elements are active switches. Energy per pulse was used to evaluate the amount of energy consumed. Two topologies were selected for evaluation: transformer output push–pull topology and half bridge output. Experimental investigation results are presented.

Introducing data-oriented theory in recent years and its successful applications in engineering and applied science and by requirements to new memory structure for managing data efficiently, lead us to present a new memory module for implementation of data-oriented models. Most of concepts in data-oriented theory are modeled as problem-solution data structure. In this paper for suitable management these kinds of data structures, a special content addressable memory with fast access is designed which is named Midpoint memory.

This paper proposes universal coarse-grained reconfigurable computing architecture for hardware implementation of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs), suitable for both field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs) implementation. Using this universal architecture, two versions of DTs (functional DT and axis-parallel DT), two versions of SVMs (with polynomial and radial kernel) and two versions of ANNs (multi layer perceptron ANN and radial basis ANN) machine learning classifiers, have been implemented in FPGA. Experimental results, based on 18 benchmark datasets of standard UCI machine learning repository database, show that FPGA implementation provides significant improvement (1–2 orders of magnitude) in the average instance classification time, in comparison with software implementations based on R project.

Based on the dual-loop control peak current mode power factor correction (PFC) converter, a feed-forward slope compensation method is proposed, which could regulate the compensated slope real-time and suppress the loop perturbation, thus controlling chaos of the system for better stability. A dual-loop Boost PFC model with the feed-forward slope compensation is built to analyze the nonlinear phenomena in system, and the corresponding circuit structure is presented. The chaos control ability of the feed-forward slope compensation is studied theoretically, and the relation of compensated slope and feed-forward signal is deduced, as well as slope stability conditions. The simulation and measured results show that this method could effectively suppress system bifurcation and chaos phenomena, and improve the system working range and dynamic response speed, and eliminate the influence on system stability for without compensated, under compensated, and over compensated.

This paper proposed an adaptive neuro-fuzzy model (ANFIS) to multilevel inverter (MLI) for grid connected photovoltaic (PV) system. The purpose of the proposed controller is that it is not requiring any optimal pulse width modulated (PWM) switching-angle generator and proportional–integral controller. The proposed method strictly prohibits the variations present in the output voltage of the cascaded H-bridge MLI. In this method, the ANFIS have the input which is grid voltage, the difference voltage and the output target is control voltage. By using these parameters, the ANFIS makes the rules and has been tuned perfectly. During the testing time, the ANFIS gives the control voltage according to the different inputs. The resultant control voltage equivalent gate pulses are utilized for controlling the insulated gate bi-polar switches (IGBT) of MLI. Then the ANFIS based MLI for grid connected PV system is implemented in the MATLAB/simulink platform and the effectiveness of the proposed control technique is analyzed by comparing with the neural network (NN), fuzzy logic control, etc. The comparison results demonstrate the superiority of the proposed approach and confirm its potential to solve the problem. A prototype of three-phase grid connected cascaded H-bridge inverter has been developed using field-programmable gate array (FPGA) and results are analyzed.

The need of effective packet transmission to deliver advanced performance in wireless networks creates the need to find shortest network paths efficiently and quickly. This paper addresses a reduced uncertainty-based hybrid evolutionary algorithm (RUBHEA) to solve dynamic shortest path routing problem (DSPRP) effectively and rapidly. Genetic algorithm (GA) and particle swarm optimization (PSO) are integrated as a hybrid algorithm to find the best solution within the search space of dynamically changing networks. Both GA and PSO share context of individuals to reduce uncertainty in RUBHEA. Various regions of search space are explored and learned by RUBHEA. By employing a modified priority encoding method, each individual in both GA and PSO are represented as a potential solution for DSPRP. A complete statistical analysis has been performed to compare the performance of RUBHEA with various state-of-the-art algorithms. It shows that RUBHEA is considerably superior (reducing the failure rate by up to 50%) to similar approaches with increasing number of nodes encountered in the networks.

It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further.

As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results.

Primary-side regulated (PSR) flyback controller has been widely used in low power charger applications for its simple structure, low cost, good electrical isolation and compact volume. However, limited by traditional primary-side sensing technology, PSR flyback controller suffers from poor dynamic response. A low standby power PSR flyback controller with fast dynamic response has been presented, and novel feedback comparison and sampler combo controlling circuit has been presented in the paper. An offline PSR controller containing the proposed speedup circuit and driving directly power bipolar junction transistor (BJT) was fabricated in Episil 1.0 μm 40 V/5 V EPI-HVCMOS process. Measured result shows that, in the entire universal input-voltage range (90 Vac–264 Vac) and 5 V 1.0 A output power, the proposed PSR controller achieves standby power less than 22 mW and average efficiency line end with 20 AWG 1.5 m up to 78%. The output voltage of the proposed PSR controller becomes stable within 3.3 ms when load current changes abruptly from 0 to 1 A and from 1 A to 0.

A low input step-up DC/DC converter and power manager in 0.18-μm CMOS process is presented. The proposed converter can work with the input voltage as low as 20 mV. The extremely low input voltage makes it suitable for energy harvesting and power management. Four logic controlled outputs provide the best voltage for various applications to accommodate low power design requirements. A low current low dropout regulator (LDO) is utilized to provide a regulated 2.2 V output for powering low power processors or other low power integrated circuit (ICs). Reserve energy on the storage capacitor CSTORE provides power when the input voltage source is unavailable, thus prolongs the life of the system and expands the application range. Extremely low quiescent current (6 μA) and high efficiency design (64%@300 μA load current) ensure the fastest possible charge times of the output reservoir capacitor. This work provides a complete power management solution for wireless sensing and data acquisition.

In this paper, a new highly linear operational transconductance amplifier (OTA) is presented. Proposed OTA employs two linearization techniques of cross-coupled double differential pairs and resistive source degeneration to achieve highly linear response under low power consumption. Considering the linearity and the frequency response issues as main parameters of OTA in the communication circuits, design procedure is theoretically formulated for the best linearity and optimum frequency compensation. Proposed OTA is simulated in 0.18-μm TSMC CMOS technology by Hspice simulator. While, the power consumption is only 467 μW, applying two-tone input voltage with amplitude of 0.6 Vp-p at 10 MHz frequency results in -61 dB third-order intermodulation (IM3) distortion of the output current that still remains below -44 dB for amplitudes up to 1 Vp-p. A precise frequency response analysis is performed which has resulted in optimum values of resistor and capacitor for miller compensation. Using common mode feedback in both stages and push-pull based output stage lead to 108 dB CMRR at DC that decreases to 84.5 dB at 100 kHz frequency.

Tri-state boost power factor correction (PFC) converter operating in pseudo-continuous-conduction mode (PCCM) is analyzed in this paper. The connection of power switch in parallel with inductor makes the boost converter operate in PCCM, which provides an additional degree of control freedom by inductor current freewheeling operation mode. Compared with boost PFC converter operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), tri-state boost PFC converter extends the load range and is therefore more suitable for wide range of load variation. However, for universal input applications, the input power factor (PF) of the tri-state boost PFC converter is relatively low when the sinusoidal reference current control strategy is used. To improve the PF over the whole input voltage range, the input current and PF expressions of the tri-state boost PFC converter is derived and the non-sinusoidal reference current control strategy is proposed. A 400 W prototype of the tri-state boost PFC converter is built by using digital signal processing (DSP) as the controller. The experimental results verify the analysis results.

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

STRIKE is an algorithm which predicts protein–protein interactions (PPIs) and determines that proteins interact if they contain similar substrings of amino acids. Unlike other methods for PPI prediction, STRIKE is able to achieve reasonable improvement over the existing PPI prediction methods. Although its high accuracy as a PPI prediction method, STRIKE consumes a large execution time and hence it is considered to be a compute-intensive application. In this paper, we develop and implement a parallel STRIKE algorithm for high-performance computing (HPC) systems. Using a large-scale cluster, the execution time of the parallel implementation of this bioinformatics algorithm was reduced from about a week on a serial uniprocessor machine to about 16.5 h on 16 computing nodes, down to about 2 h on 128 parallel nodes. Communication overheads between nodes are thoroughly studied.

The paper presents new single active element based second order band pass filters. The new circuits use single dual-X current conveyor with buffered output and five passive components. The proposed circuits enjoy the features of high input impedance and low output impedance, which are desirable features for voltage-mode circuits. Circuit operation at high frequencies are verified along with non-ideality and parasitic study. The Monte Carlo analysis is also done which justify good sensitivity performances of the proposed circuits. Routh–Hurwitz's stability test is performed to verify the stability of the proposed circuits. For showing the integration aspect, resistorless band-pass filters are also realized. The proposed low-Q filters are useful for cascading. The feature of cascadability is further utilized by showing an application of fourth-order band-pass filter. The performances of the proposed circuits are depicted through Personal Simulation Program with Integrated Circuit Emphasis (PSPICE) simulations, which show good agreement to theoretical applications. The new circuits are expected to enhance the already existing knowledge on the subject.

This paper proposes a new blind approach for time synchronization of orthogonal frequency division multiplexing (OFDM) receivers (RX). It is largely known that the OFDM technique has been successfully applied to a wide variety of digital communications systems over the past several years — IEEE 802.16 WiMax, 3GPP-LTE, IEEE 802.22, DVB T/H, ISDB-T, to name a few. We focus on the synchronization for the ISDB-T digital television system, currently adopted by several South American countries. The proposed approach uses the coarse synchronization to estimate the initial time reference and then, the fine synchronization keeps tracking the transmitter (TX) time reference. The innovation on the proposed approach regards to the closed loop control stabilization of the fine synchronization. It uses a smith predictor and a differential estimator, which estimates the difference between TX and RX clock frequencies. The proposed method allows the RX to track the TX time reference with high precision ( sample fraction). Thus, the carriers phase rotation issue due to incorrect time reference is minimized, and it does not affect the proper RX IQ symbols demodulation process. The RX internal time reference is adjusted based on pilot symbols, called scattered pilots (SPs) in the context of the ISDB-T standard, which are inserted in the frequency domain at the inverse fast Fourier transform (IFFT) input in the TX. The averaged progressive phase rotation of the received SPs at the fast Fourier transform (FFT) output is used to compute the time misalignment. This misalignment is used to adjust the RX fine time synchronism. Furthermore, the proposed method has been implemented in an ISDB-T RX. The FPGA-based receiver has been evaluated over several multipath, Doppler and AWGN channel models.