Journal of Circuits, Systems and Computers

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications.

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.

This paper presents a voltage-mode (VM) tunable all-pass section, employing a grounded capacitor and a newly introduced current conveyor with an extra X stage. The proposed all-pass filter uses grounded capacitor as the only passive component and benefits from high input and low output impedance. The proposed circuit exhibits eight performance features without trade-offs, as compared to carefully chosen 25 published works. The functionality of the proposed element is verified through PSPICE simulation using 0.25-μm process parameters. An application of second order is also incorporated.

This paper analyzes the structural controllability of active networks by using the conclusions drawn from the structural controllability of an active network over F(z). This analysis method only requires the drawing of a controlling flow graph that is based on the circuit schematic diagram of active networks. Therefore, it is both straightforward and intuitive to use such an approach. First, second-order active RC networks are analyzed and designed by using this method. Additionally, state feedback circuits are designed based on linear system theory. Finally, the experiment results show that the pole assignment can be realized to meet the requirements of stability and dynamic performance, which were set out in the design of the state feedback.

In this work we propose a game theory (GT)-based global router. It works in two steps: (i) Initial routing of all nets using maze routing with framing (MRF) and (ii) GT-based rip-up and reroute (R&R) process. In initial routing, the nets are divided into several small subsets which are routed concurrently using multithreading (MT). The main task of the GT-based R&R process is to eliminate congestion. Nets are considered as players and each player employs two pure strategies: (attempt to improve its spanning tree, and, do not attempt to improve its spanning tree). The nets also have mixed strategies whose values act as probabilities for them to select any particular pure strategy. The nets which select their first strategy will go through the R&R operation. We also propose an algorithm which computes the mixed strategies of nets. The advantage of using GT to select nets is that it reduces the number of nets and the number of iterations in the R&R process. The performance of the proposed global router was evaluated on ISPD'98 benchmarks and compared with two recent global routers, namely, Box Router 2.0 (configured for speed) and Side-winder. The results show that the proposed global router with MT has a shorter runtime to converge to a valid solution than that of Box Router 2.0. It also outperforms Side-winder in terms of routability. The experimental results demonstrated that GT is a valuable technique in reducing the runtime of global routers.

The segmented channel routing problem is fundamental to the routing of row-based field programmable gate arrays (FPGAs) and is proven to be nondeterministic polynomial time (NP) complete. In this paper, we capitalize on the compelling advancements in satisfiability (SAT) solvers to propose a multilevel pseudo-Boolean SAT-based approach. We construct several levels of hierarchy amongst the nets and the routing problem of each level is formulated as a pseudo-Boolean optimization (PBO) problem. Moreover, an optimization technique of reducing the number of variables in PBO problems is described to improve the scalability of the proposed method. Similar to the SAT-based routing, the unroutability of a given circuit can be proved by the approach. Experimental results show that the proposed method compares very favorably with existing algorithms and achieves the best convergence rate.

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

A new voltage-mode (VM) multifunctional filter using only two voltage followers (VFs), two resistors and two capacitors is proposed. The proposed filter with two inputs and two outputs can provide low-pass (LP) and high-pass (HP) responses. It does not need any critical passive component matching constraints. Additionally, it has low output impedances, low power dissipation and adequately low THD values. However, it does not have high input impedances; accordingly, it requires an extra VF to obtain high input impedance. A number of time domain and frequency domain simulations and experimental tests are performed to verify the claimed theory.

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm².

For that the conclusion of maximum matching is an important basic theory for controllability of complex networks, we first study the validity of maximum matching for fractional-order directed complex networks. We also develop a new analytical tool to study the controllability of an arbitrary fractional-order directed complex directed network with self loop by identifying the set of driver nodes with time-dependent control that can guide the system's entire dynamics. Through analyzing a mass of typical examples, we propose a new theory named “variant maximum matching” which is superior to the old one. Finally, we present some typical examples to prove the correctness of our conclusions.

In this paper, simple approach to analyzing the starting procedure of synchronous motors (SMs) is presented with an emphasis on the pull-in process. Instead of the classical, mostly intuitive pulling-repelling torque approach, an analytical method based on the motor mechanical part swing equation is employed. Factors affecting starting and pull-in processes are clearly indicated and torque impulse balance leading to a pull into step is revealed. It is shown that if the motor fails to pull into step within a single oscillation, it can still be synchronized during one of the succeeding acceleration periods. The crucial role of the excitation winding energizing instant is demonstrated as well. Moreover, the revealed similarity between the SM and phase locked loop (PLL) operations, leads to the conclusion that the algorithms use for analyzing the operation of one may be employed for investigating the other. Experimental results are given to demonstrate the different scenarios, mentioned in the manuscript.

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm² core area and consumes 3.6 μA from a 1 V supply.

Implantable wireless neural recording microsystems have demonstrated their efficacies in neuroscience studies in the past decades. However, with the advances of neurobiology, higher sensitivity and higher precision neural recording microsystems are becoming the critical need. A biopotential amplifier is the first stage of a neural recording microsystem, the performance of which decides the signal-to-noise ratio and the power dissipation of each recording-channel. In this paper, we present a low-noise biopotential amplifier with a noise efficiency factor (NEF) optimized closer to the theoretical limit of a folded cascode structure. A high transconductance input nMOSFET pair is designed to guarantee a low input-referred noise. A self-biased scheme comprising a weak positive feedback and a strong negative feedback is employed to further enhance the transconductance. By optimizing the noise performance while maintaining the NEF value close to the theoretical limit, a very low input-referred noise and a higher power-noise efficiency are achieved in our design. Using a standard 0.13-μm CMOS process, the proposed amplifier achieves an input-referred noise of 1.98 μV_rms at the expense of 7.5 μW power, corresponding to a NEF of 2.31. The gain of the proposed amplifier is 40.84 dB at a -3 dB bandwidth from 6.65 Hz to 9.38 kHz.

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step method. The parity-preserving gate constructed by the two-step method has characteristics of low quantum cost because the quantum representation obtained from the counterexample for a given function in each step has the minimum quantum cost. In order to further reduce the quantum cost and decrease the synthesis time, the semi parity-preserving gates are put forward for the first time. These gates are parity-preserving when the auxiliary input is set to 0 and opposite parity when 1. Maintaining good robustness of the system in performing specific function, semi parity-preserving gate is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits. The innovation of this paper is introducing the formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates.

A novel class of cascaded-integrator-comb (CIC) filter functions, which preserve the CIC filter simplicity avoiding the multipliers, is proposed in this paper. The proposed class is designed using several cascaded non-identical CIC sections. The paper provides its non-recursive and recursive forms, as well as frequency response. Compared with classical CIC finite impulse response (FIR) filters designed novel class shows excellent performances in term of insertion loss in stopband and selectivity. To verify the behavior of the proposed novel class of CIC FIR filter functions, several illustrative examples are provided. Also, comparisons of the novel filter class with existing classical CIC structures and some recent improvements given in the literature are provided. For the same level of a constant group delay of 31.5 s, a classical CIC filter function has insertion loss of 115.176 dB, and proposed novel filter function has 136.757 dB. It has achieved significant improvement of 21.581 dB or approximately about 20%.

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.