Journal of Circuits, Systems and Computers

Content addressable memory (CAM) can perform high-speed table look-up with bit level masking capability. This feature makes CAMs extremely attractive for high-speed packet forwarding and classification in network routers. High-speed look-up implies all the CAM word entries to be accessed and compared with a search word to find a suitable match in a single clock cycle. This parallel search activity requires large energy consumption which needs to be reduced. In this paper, a review of the energy reduction techniques of CAM is presented. A comparative study of some popular techniques has been made with the help of simulations carried out in this work and published results.

Dictionary learning (DL) algorithms have shown very good performance in face recognition. However, conventional DL algorithms exploit only the training samples to obtain the dictionary and totally neglect the test sample in the learning procedure. As a result, if DL is associated with the linear representation of test sample, DL may be able to perform better in classifying the test samples than conventional DL algorithms. In this paper, we propose a test sample oriented dictionary learning (TSODL) algorithm for face recognition. We combine the linear representation (including the $l_0$-norm, $l_1$-norm and $l_2$-norm) of a test sample and the basic model of DL to learn a single dictionary for each test sample. Thus, it can simultaneously obtain the dictionary and representation coefficients of the test sample by minimizing only one objective function. In order to make the learning procedure more efficient, we initialize a dictionary for the new test sample by selecting from the dictionaries of previous test samples. The experimental results show that the TSODL algorithm can classify test samples more accurately than some of the state-of-the-art DL and sparse coding algorithms by using a linear classifier method on three public face databases.

Nowadays, it is desirable to generate traffic which can reflect realistic network traffic environment for performance evaluation of network equipments. Existing traffic generation solutions mainly include special test equipments, software traffic generators and field programmable gate array (FPGA)-based traffic generators. However, special test equipments are generally too expensive, software traffic generators could not achieve high data rates and FPGA-based traffic generators mostly lack flexibility. This paper presents a novel traffic generation solution according to an aggregated process-based model to overcome the weakness of above methods. The traffic generator can generate real-time Poisson, two-state Markov-modulated Poisson process (MMPP-2) and self-similar traffic by hardware. The main structure of the traffic generator is presented and statistical properties of the generated traffic have been evaluated. Experiment results indicate that the proposed traffic generation solution can achieve better performance of the generated traffic compared with existing FPGA-based traffic generators while the required date rates can be up to Gbps line rate.

This paper introduces a new method based on the finite impulse response (FIR) filter and inverse discrete wavelet transform (IDWT) in order to separate the fundamental component from the non-ideal load voltage. Then, the proposed method is applied to the single-phase shunt active power filter. The presented simulation and experimental results show that in the suggested indirect method (IM), the compensation of the load current will continue correctly even under non-sinusoidal load terminal voltage. For this purpose the fundamental component of load terminal voltage is extracted by the new proposed method, and the second-order generalized integrator (SOGI) is used for improving the total harmonic distortion (THD) of the source side current. The operations of the proposed control method are confirmed by the simulations and experimental results using MATLAB software and the laboratory prototype, respectively.

In this paper, a developed configuration for multilevel voltage source inverters (MVSIs) is proposed. The proposed topology can be used as symmetric and asymmetric inverters. In asymmetric mode, DC source magnitudes are defined in a way that the number of output levels gets more than the case when the symmetrical DC sources are applied. In this regard, to calculate the required magnitudes of DC voltage sources several different solutions are proposed. In multilevel inverters, the overall costs, circuit size and installation area, complexity of control scheme and reliability are directly dependent on the number of circuit devices needed. The provided comparison study among suggested inverter in all defined solutions, cascaded H-bridge (CHB) and recently proposed converters, validates that the proposed inverter uses reduced number of circuit devices. The given simulation results confirm the feasibility of the proposed modular structure. Also, to approve the practicability of the proposed inverter, a prototype of the proposed topology has been implemented. Finally, simulation and experimental results are compared with each other and the provided comparison shows that the obtained results are in good agreements.

This paper presents low-cost velocity and position control of a double-sided linear switched reluctance motor (LSRM). This investigation gives a detailed presentation of modeling, simulation and experimental results as well as open and closed loop controls. In addition, control strategy was achieved by the help of proportional-integrator (PI) controller in order to ensure smooth motion with highly reduced position and force oscillations. For low-cost purposes, PIC18F452 control board and inverter-based MOSFET are used. This simple approach helps to integrate the actuator in high precision industrial applications. Comparison between simulation and experiment results gives a good agreement.

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18$\mu$m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68k$\mathrm{\Omega }$, respectively. Time domain analysis shows that for an input signal of 20$\mu$A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only $17.1\times 36.9\mu {\mathrm{\text{m}}}^2$.

Cuckoo search optimization (CSO) algorithm, a recently proposed metaheuristic, has shown promising results in various problem domains. Results from recent studies show that engineering and tuning discrete cuckoo search optimization’ parameters is a daunting task. In this paper, an attempt to enhance the performance of the CSO algorithm in solving discrete combinatorial optimization problems is presented. Performance of the discrete modified CSO algorithm is compared with genetic algorithm (GA), particle swarm optimization (PSO), hybrid of GA/PSO, and simulated annealing. In addition, a memetic algorithm (MA) that combines discrete modified CSO and tabu search is proposed. Results show that the proposed improvements help in enhancing the performance of the original algorithm. As a test case, the NP-hard problem of buffer minimization in CMOL (CMOS+nanowire+MOLecules) circuits is addressed. The performance of the proposed implementation of CSO algorithm is compared with other heuristics.

Between fault detection and diagnostic test, there are many tests with varying degrees of diagnosability. There is trade-off between diagnosability of the test and its length. High diagnosability test is longer and takes more time. In this work, we tried to balance both by generating test slightly longer than normal detection test but with high diagnosability, without affecting fault coverage. The order of test vector application to attain more fault and diagnostic coverage in fewer test patterns is also mentioned. If more diagnosability is required, test vectors till the lower order should be used, whereas shorter test compromises on diagnosability. Our results show similar distinguishing capability as compared with a recent work but with 90% reduction in normalized time. The fault model used in this work is stuck-at fault model.

The regards to widespread impact of distribution networks and ever increasing demand for electricity, some strategies must be devized in order to well operate the distribution networks. In this paper, to enhance the accountability of the power system and to improve the system performance parameters, simultaneous placement of renewable energy generation (REG) sources (e.g., wind, solar and dispatchable distributed generators (DGs)) and capacitors are investigated in a modified radial distribution network with considering ZIP loads. To enhance all network parameters simultaneously to the best possible condition multi-objective functions are proposed and solved using non-dominated sorting genetic algorithm (NSGA II). The employed objectives contain all economical, environmental and technical aspects of distribution network. One of the most important advantages of the proposed multi-objective formulation is that it obtains non-dominated solutions allowing the system operator (decision maker) to exercise his/her personal preference in selecting each of those solutions based on the operating conditions of the system and the costs. It is clear that the implementation of each non-dominated solution needs related costs according to the technology used and the system performance characteristics. However, there is a paucity of objective methodologies for ranking the obtained non-dominated solutions considering economical, environmental and technical aspects. So, in this paper, data envelopment analysis (DEA) is suggested for this purpose. In other words, in this paper, first NSGA II is applied to the siting and sizing problem, and then the obtained non-dominated solutions are prioritized by DEA. The significant advantage of using DEA is that there is no need to impose the decision maker’s idea into the model and ranking is done based on the efficiencies of the non-dominated solutions. The most efficient solution is the one which has improved network parameters considerably and has lowest costs. So, using DEA gives a realistic view of solutions and the provided results are for all, not for a specific decision maker. To validate the effectiveness of the proposed scheme, the simulations are carried out on a modified test case 33-bus radial distribution network.

Cryptographic hash functions are at the heart of many information security applications like message authentication codes (MACs), digital signatures and other forms of authentication. One of the methods to ensure information integrity is the use of hash functions, which generates a stream of bytes (hash) that must be unique. But most functions can no longer prevent malicious attacks and ensure that the information have just a hash. Because of the weakening of the widely used SHA-1 hash algorithm and concerns over the similarly-structured algorithms of the SHA-2 family, the US National Institute of Standards and Technology (NIST) has initiated the SHA-3 contest in order to select a suitable drop-in replacement. KECCAK hash function has been submitted to SHA-3 competition and it belongs to the final five candidate functions. In this paper, we present the implementation details of the hash function’s KECCAK algorithm, moreover, the proposed KECCAK design has been implemented on XILINX FPGAs. Its area, frequency, throughput and efficiency have been derived and compared and it is shown that the proposed design allows a trade-off between the maximum frequency and the area implementation.

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A $16\times 16$ bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence${}^{\text{®}}$ EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during the design, so that the search process for finding the optimal system configurations will be rapid and more efficient. The Bayesian belief network (BBN)-based modeling framework for design space pruning proposed in this paper attempts to resolve the existing limitation in imparting domain knowledge and provides a pioneering effort to support the designer during the process of application specific system design. The Xtensa customizable processor architecture from Tensilica and a very long instruction word (VLIW) processor architecture are considered as example target platforms to impart the domain knowledge for the proposed model. Case studies in support of the proposed model are presented in order to understand how BBN can be used for design space pruning by propagating the evidence and arriving at probabilistic inferences to ease the decision-making process. The results show that the design space reduces drastically from a few million design options available to just less than one hundred for Xtensa architecture and from a few billions of design options available to just few thousands for VLIW architecture. The work also validates the pruned design points for their optimality.

Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

Object tracking in real-time is one of the applications of video processing, where the required computational cost is high due to intensive high data processing. In order to solve these problems, this paper presents an embedded solution, where the Hardware/Software (HW/SW) co-design architecture is used for the implementation of well-known kernel-based tracking system. In this algorithm, the target is searched in consecutive frame by maximizing the statistical match with similarity estimation of color distribution. The whole tracking system is implemented on low cost Field Programmable Gate Array (FPGA) device with image resolution of 1280$\times$720 pixels and target window size of 160$\times$80 pixels. The HW/SW co-design architecture is proposed to accelerate the computational speed of the system. The performance of the system is evaluated in terms of execution speed and frame rate compared with software based implementation. The hardware cost of design is also compared with other existing methods. The proposed design achieves 22 times computational speed and maximum 60 Frames Per Second (FPS) compared with software based design.

This paper proposes the photovoltaic (PV) interfaced static synchronous compensator (STATCOM) for voltage and frequency control of wind turbine driven self-excited induction generator (SEIG) system. The PV interfaced STATCOM mainly is used for sustainable control of load voltage and frequency of the SEIG system. In addition, PV based STATCOM acts as reactive power compensator, harmonic eliminator and load balancer under balanced/unbalanced nonlinear loads. The energy storage system is incorporated to PV based STATCOM to sustain the active power under variable wind power. The proposed control method extracts the reference current with the use of fuzzy logic controller (FLC) employed in alternating current (AC) voltage control loop. The proposed topology utilizes the PV energy with an energy storage unit to meet the active power requirement of the wind power generating system. Besides, it exports the power generated in the PV system to the load during the unavailability of wind. The PV based STATCOM controlled SEIG system is subjected to different types of loads in order to assess the performance of the system under steady-state and dynamic conditions. The results obtained from the simulation and experimental setup are analyzed to ensure the performance of the proposed controller.

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided.