Journal of Circuits, Systems and Computers

Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gating (CG) has been proposed for finite state machines (FSMs). The CG logic is based on the idea of dynamically disabling the clock signal to the sequential blocks of the FSM during periods of inactivity. The inactive state is decided by the occurrence of self-loops within the FSM. The proposed gating technique operates at a fine level of granularity and can be generally implemented to any FSMs. A technique of partitioning the registers of the FSM is introduced in this work in order to avoid functional errors and signal losses during gating. The logic of registers partitioning for CG in large FSMs containing few or no self-loops is also presented in this work. The simulation results obtained shows up to 38% (max) dynamic power reduction of the FSM with a little penalty in area. The timing slack associated with the gated and non-gated FSMs is also analyzed for varying clock frequencies. The results indicate a minimal increase in delay after gating. The technique for CG in large FSMs containing few or no self-loops has yield up to 58% (max) power reduction.

This paper presents a new voltage-mode (VM) universal biquadratic filter using differential difference current conveyor transconductance amplifier (DDCCTA) as an active element. The circuit employs one DDCCTA, two floating resistors and two floating capacitors which can realize five biquadratic filters, namely low-pass (LP), band-pass (BP), band-stop (BS), high-pass (HP) and all-pass (AP) into one single topology. For realizing these filtering functions, passive component-matching conditions, inverting-type and/or doubling-input signal requirements and changing circuit configuration are absent. The natural angular frequency and quality factor of the filter can be orthogonally controlled deliberately. The VM biquadratic filter using grounded passive components with high-input and low-output impedances can be obtained by adding an additional DDCCTA or differential difference current conveyor (DDCC). The simulation results with 0.5$\mu$m CMOS process from MIETEC are given to confirm the theoretical predictions and the experimental results are also included to verify the workability of the proposed structure.

In this paper, a new active current-mode (CM) minimal component, cascaded current differencing unit (CCDU) and a CM nth-order filter based on the CCDU have been presented. The proposed CCDU simplifies the design of the CM nth-order filter circuit considerably. The proposed nth-order circuit, which adopts only an active component and n grounded capacitors, can simultaneously realize low-pass (LP), band-pass (BP) and high-pass (HP) filter responses. It enjoys the simple configuration and is suitable for integrated circuit (IC) fabrication. PSPICE simulations and experimental tests for CM third-order filter based on this structure have also been conducted and the results have good agreement with the theoretical analysis.

In this paper, performance enhancement of Photovoltaic (PV) system is done by a passive lossless soft switched noninverting Cuk converter with Perturb and Observe (P&O) based maximum power point tracker (MPPT) that uses a hybrid sliding mode controller (SMC). In the proposed Cuk converter, conduction losses, voltage stress and switching losses are mitigated by introducing a snubber cell. Therefore, Cuk converter efficiency is improved which in turn increases efficiency of PV system. Peak power is continuously collected from PV panel and optimal operating point is detected using hybrid SMC based MPPT method. Performance analysis of the modified Cuk converter and conventional converter is illustrated by simulation and experimental methods for various irradiation and temperature changes. Experimental results verify the performance of modified Cuk converter implemented in PV system.

Among different implementations of the Advanced Encryption Standard (AES) S-box, the implementation based on composite field arithmetic (CFA) has the smallest size. In this study, to eliminate the redundant gates in the implementation of CFA-based S-box, a new optimization algorithm named common subexpression elimination (CSE)–shortest critical path constructing (SCPC) algorithm is proposed. The CSE–SCPC algorithm combines an efficient CSE technology with the SCPC method, therefore not only area cost but also the delays are taken into account in the optimization process. For facilitating the search of common subexpressions (CSs), the main operation of CFA-based S-box — the multiplicative inverses (MI) over galois field (GF)((2${}^4{)}^2)$ — is divided into six parts and each part is expressed by logical expressions directly. Furthermore, the parts with same input are classified into the same group, as there are CSs among them. Each part of the S-box is optimized by the CSE–SCPC algorithm. For the MI over GF((2${}^4{)}^2)$, both the CSs in each part and the CSs among the parts are eliminated by the CSE–SCPC algorithm. Compared to the previous works, our design has not only the minimal area cost but also the shorter critical path in both theoretical computing evaluation and experimental evaluation.

This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5$\mu$m CMOS process, which has a conversion rate of 43.48kS/s with oversampling ratio (OSR) of 23 and achieves 84.83dB SNDR and 13.799-bit ENOB. It consumes 2.4mW with a 5V voltage supply, and the FOM is 3.87pJ/step.

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.

This contribution proposes a precoder-decoder design aiming to improve the performance of multiple-input–multiple-output (MIMO) detectors under correlated fading channels. The MIMO detection principle namely minimum mean squared error (MMSE) detector is analyzed under such channel condition. The proposed approach deploys the channel state information (CSI) aiming to estimate the level of spatial correlation channel, namely normalized correlation index $\rho$ and uses this information to improve the MIMO system performance. Furthermore, the impact of the $\rho$ estimation errors on the performance, as well the performance degradation for different levels of correlation have been analyzed and compared with the classical MMSE-MIMO detector operating under uncorrelated channels and perfect channel estimation.

In this paper, a new first-order current-mode (CM) universal filter employing two dual output second-generation current conveyors (DO-CCIIs), one resistor and a grounded capacitor is proposed. The proposed filter has low input and high output impedances; thus, it can be easily connected with other CM circuits. It can simultaneously realize first-order low-pass (LP) and all-pass (AP) responses and can provide high-pass (HP) response with interconnection of LP and AP responses. It can be tuned electronically by replacing with dual output second-generation current controlled conveyors (DO-CCCIIs) instead of DO-CCIIs and removing the resistor. It has only a resistor but no capacitor connected in series to X terminal of DO-CCII; accordingly, it can be operated at high frequencies. Also, it does not need any critical passive component matching conditions and cancellation constraints. A number of simulation results based on SPICE program are included to exhibit performance, workability and effectiveness of the proposed filter configuration.

In this paper, we address the problem of angle estimation in a bistatic multiple-input multiple-output (MIMO) radar which exploits nonuniform linear array at both the transmitter and the receiver with small number of antennas. It is demonstrated that the conventional trilinear decomposition-based angle estimation algorithm can identify only a comparatively small number of targets under this condition. In order to increase the number of identifiable targets, we derive an expanded trilinear decomposition-based angle estimation algorithm for MIMO radar, which can expand the size of the trilinear model. The proposed algorithm not only has the advantages of not requiring spectral peak searching, nor additional pair matching and being suitable for nonuniform arrays, but also identifies more targets than the conventional trilinear decomposition-based angle estimation algorithm under the same conditions. Moreover, the angle estimation performance of the proposed algorithm is better than that of the conventional trilinear decomposition-based angle estimation algorithm and the estimation of signal parameters via rotational invariance techniques (ESPRIT) algorithm. Simulation results illustrate the effectiveness and improvement of the proposed algorithm.

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

This paper describes the design of a self-tuning OTA-C notch filter (NF), based on a phase control loop concept. The phases of filter input and output signals are compared and the phase error is used to generate the control voltage, which adjusts the transconductances of operational transconductance amplifiers (OTAs) and, consequently, tunes the NF center frequency without quality factor variation. The proposed solution is robust to filter parameter variations. The filter is implemented in 0.13$\mu$m SiGe BiCMOS technology. Under the typical circuit operating conditions, the center frequency tuning is within the range from 70MHz up to 150MHz, with tuning error less than 1%. The power consumption is less than 3.6mW, the 1dB gain compression point is $-$2.5dBm, the input (IIP3) and output (OIP3) intercept points are 3.47 and 9.07dBm, respectively, and the total filter effective noise voltage is 4.35$\mu$Vrms. The filter structure is suitable for complementary metal-oxide-semiconductor (CMOS) implementation.

In this paper, photovoltaic (PV) system interfaced single-phase shunt active power filter (SAPF) is proposed to supply uninterrupted and clean power to small-scale industries and domestic customers. The second-order generalized integrator (SOGI) is employed to extract the reference current of PV-SAPF. The proposed topology does not need voltage measurement and sensors on both the AC and DC side, just two current sensors are accustomed to measure converter and load currents. To be able to acquire an accurate reference source current, the distorted load is only processed through the SOGI control algorithm which does not need voltage-related information. The PV interfaced SAPF mainly is used for sustainable compensation of current disturbances and voltage interruption of the single-phase distribution system. The proposed topology utilizes the PV energy with an energy storage unit to meet the active power requirement of the utility grid. Besides, it exports the power generated in the PV system to the load during unavailability of grid supply. The PV-SAPF system subject to different types of loads can assess the performance of the system under steady-state and dynamic conditions. To validate the effectiveness of the proposed controller for PV interfaced SAPF, the simulation and experimental results are presented.

Satisfiability modulo theories (SMT) is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT can be well tuned to solve several of the most intriguing problems in electronic design automation (EDA). Analog placers use physical constraints to automatically generate small sections of layout. The work presented in this paper shows that SMT solvers can be used for the automation of analog placement, given some physical constraints. We propose a tool that uses Microsoft Z3 SMT solver to find valid placement solutions for the given analog blocks. Accordingly, it generates multiple layouts that fulfill some given constraints and provides a variety of alternative layouts. The user has the option to choose one of the feasible solutions. The proposed system uses the quantifier-free linear real arithmetic (QFLRA), which makes the problem decidable. The proposed system is able to generate valid placement solutions for benchmarks. For benchmarks that have many constraints and few geometries, the proposed system achieves a speedup that is 10 times faster than other recently used approaches.

The synthesis of voltage-mode parameter tunable biquadratic bandpass filters using grounded capacitors is presented. To easily construct high-order filters, the synthesis of voltage-mode cascadable tunable biquadratic bandpass filters is also indicated. The synthesis procedure is based on the nodal admittance matrix (NAM) expansion method using nullor–mirror pathological elements. The synthesis of filters using grounded capacitors is considered since it is helpful for easing the elimination/accommodation of various parasitic effects for monolithic integration. The Q factor of the derived filters can be adjusted without changing the natural frequency, so the high-Q bandpass filters are attainable. The workability of some synthesized circuits is verified by HSPICE simulations.

This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(2⁴) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).