Journal of Circuits, Systems and Computers

Large scale synchronous network-on-chip (NoC) requires complex clock tree design, which leads to a large area overhead and power consumption. Based on handshaking protocols, asynchronous NoC does not have global clock tree distribution, which results in a natural power saving mode without any explicit clock gating. However, the faults occurring in such asynchronous networks will seriously affect their performances. In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed router is able to detect the faults of ports and links. Then, a fault-tolerant routing mechanism, based on the port priority in different quadrants, is proposed to maximize the number of packets that can be transmitted via the shortest paths. In this way, the fault-tolerance of asynchronous routers can be achieved. Besides that, AFTER could also achieve high scalability, and is suitable for the large scale globally asynchronous locally synchronous (GALS) system. The experimental results show that, when faults occur in the network, AFTER has a better fault-tolerance performance than the reference.

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18$\mu$m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1GHz UWB LNA accomplishes a maximum gain of 14.26dB with only 2.33mW power consumption at 0.8V supply voltage, while Noise Figure (NF) is 1.49–3.41dB and the chip area is 0.46mm² including test pads (core area is 0.23mm²).

A new approach to the design of a comb filter using current conveyor is proposed to eliminate the undesired harmonic interference from biomedical signal. In this approach, a number of inverted band pass filters are used to construct a comb filter. The components used are second generation current conveyor (CCII), capacitor and resistor. To verify the performance of the proposed circuit, the comb filter is designed to eliminate the unwanted power line frequency of 60Hz and its odd harmonics such as 180, 300 and 420Hz. The proposed circuit is simulated by implementing CCII$\pm$ using a macro model of commercially available CFOA IC AD844 as well as 0.18$\mu$m CMOS technology. The circuit is also verified experimentally by using commercially available IC AD844. The effectiveness of harmonic removal has also been tested.

In this paper, a fully integrated Ku-band voltage controlled oscillator (VCO) with low phase noise is presented in a GaAs heterojunction bipolar transistor (HBT) technology. A cross-coupled configuration is employed to achieve low phase noise, and to achieve high output power, the largest HBT and higher bias current are adopted. The implemented VCO demonstrates that the oscillation frequency is from 13.77GHz to 14.8GHz, with a maximum 4.83dBm output power at 13.77GHz. The phase noise of the VCO is $-$100.2dBc/Hz at 1MHz offset from 14.36GHz oscillation frequency. The VCO consumes 61.2mW from 6V supply and occupies an area of 0.51mm$\times 0.62$mm. Finally, the figure-of-merits (FOMs) for VCOs are discussed.

This paper proposes a realistic model of magnetizing branches for transient calculation of electric power circuits. The model represents the nonlinear relationship between flux linkage and exciting current of magnetizing branches with a major loop and a family of minor loop trajectories, which has the capability of simulating the multi-valued hysteresis behavior. By applying the proposed model to transient calculation, an efficient algorithm is developed for obtaining the transient responses in electric power circuits. In the algorithm, the electric power circuit is divided into the magnetizing branches and the remaining linear part. The nonlinear differential equations are set up for the magnetizing branches and solved by the semi-explicit Runge–Kutta method. The transient calculation for the remaining linear part is performed on the basis of the solution to the magnetizing branches. Then, a laboratory measurement is made with a reduced-scale experimental arrangement. The measured results are compared with the calculated ones and a reasonable agreement is shown between them.

Threshold voltage self-compensation technology (TVSC) has been widely used in RF energy harvester. In this paper, the influence of the size of rectifying transistors, the stages and compensation orders of the rectifier, and the impedance matching network on the performance of RF energy harvester has been studied. A dual band RF energy harvester with hybrid threshold voltage self-compensation (HTVSC) is proposed in this paper in 65-nm CMOS process according to the distribution characteristic of the ambient RF energy. By combining TVSC and the technology of weak forward bias between the source and body of the rectifying transistor, the threshold voltage of MOSFET can be dramatically decreased. The performance of the RF energy harvester has been improved using this new technology. The simulation results show that the proposed dual band RF energy harvester can acquire energy at the band of 900MHz and 2.4GHz. At 900MHz-band (825–960MHz), with 1M$\mathrm{\Omega }$ load resistor, the output voltage of the energy harvester can be over 1.0V with a minimum $-$18dBm RF input power and a maximum 13.8% power conversion efficiency (PCE). At 2.4GHz-band (2.4–2.485GHz), the minimum input power can be as low as $-$19dBm with a maximum efficiency of 16.8%.

Power Quality Assessment (PQA) is a critical issue both in transmission and distribution networks. Therefore, it is necessary to precisely classify the disturbances in shortest possible time to prevent the malfunction or increase of losses in the electrical equipment through appropriate remedial techniques. This paper proposes a highly accurate method of PQA through data acquisition using smart sensors, the Rogowski coils (RCs). RCs with wide band width and linear characteristics allow faithful reproduction of high-frequency (HF) signals. In the proposed method, simulated disturbance signals are applied to RC. The output signals are subjected to multilevel wavelet decomposition and then computation of the energy difference in the detailed components between the disturbance signal and the pure sinusoidal waveform is performed to design a fuzzy logic Power Quality Classifier. The classifier is tested by varying the magnitude, frequency and duration of the disturbance and found to be accurate to 98.38%. The classification accuracy depends mainly on the performance of sensors at HFs. Thus, with RCs as sensors instead of conventional instrument transformers, it is found that the precision of power quality classification is greatly improved.

This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100–900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design.

In this paper, a novel GSA technique is used for improving the voltage stability of the system with multiple FACTS devices. The proposed novel algorithm is used to optimize the location, size and number of FACTS devices. The GSA is enhanced with the use of boundary for optimizing the parameters of the system. Therefore, the voltage stability is improved while satisfying a given set of operating and physical constraints. Here, multiple FACTS devices are used to evaluate the performance of proposed algorithm and these devices are connected in single line and double line of the bus system. The optimal locations and power ratings of the FACTS devices are determined, based on the voltage collapse rating and power loss of the system. The proposed technique is implemented in MATLAB platform and tested with IEEE 30 bus system. The performance of the proposed method is evaluated by locating multiple FACTS devices and compared with the PSO-adaptive GSA and GA-GSA technique.

A low-voltage low-power Sigma-Delta modulator for health monitoring system is designed using a standard 0.18$\mu$m CMOS technology. To achieve high accuracy with low power consumption in low supply voltage environment, the designed modulator is implemented with a one-bit third-order topology, in which the input-feedforward structure and switched-opamp (SO) technique are combined. Using the proposed design method, the SO meets the system requirements with the minimal power consumption and good stability in a feedback loop. The modulator achieves 86dB dynamic range (DR) over a 300Hz bandwidth with an oversampling ratio (OSR) of 128, while it occupies 0.16mm² and consumes 12$\mu$W under a 1.1V supply.

Self-excited induction generators (SEIG) are found to be most suitable candidate for wind energy conversion application required at remote windy locations. The major drawbacks of these generators are the poor voltage and frequency control under load and prime mover speed perturbations. In this paper, an attempt has been made to optimize the control strategy under various load and prime mover conditions, of the self-excited wound rotor induction generator (SEWRIG). By tolerating a slight deviation of the output voltage and ensuring a constant frequency with an adequate external rotor resistance, only four values of excitation capacitor are required for the whole range of operation. The effectiveness of the adopted strategy has been confirmed by comparing on a 0.8-kW wound rotor induction generator the simulated results to the corresponding obtained with an experimental test. A close agreement between the computed and experimental results confirms the efficiency of the adopted method.

This paper concerns the design of an observer-based repetitive control system (RCS) to improve the periodic disturbance rejection performance. The periodic disturbance is estimated by a repetitive learning based estimator (RLE) and rejected by incorporation of the estimation into a repetitive control (RC) input. Firstly, the configuration of the observer-based RCS with the RLE is described. Then, a continuous–discrete two-dimensional (2D) model is built to describe the RCS. By choosing an appropriate Lyapunov functional, a sufficient condition is proposed to guarantee the stability of the RCS. Finally, a numerical example is given to verify the effectiveness of the proposed method.

Shared cache interference in multi-core architectures has been recognized as one of major factors that degrade predictability of a mixed-critical real-time system. Due to the unpredictable cache interference, the behavior of shared cache is hard to predict and analyze statically in multi-core architectures executing mixed-critical tasks, which will not only result in difficulty of estimating the worst-case execution time (WCET) but also introduce significant worst-case timing penalties for critical tasks. Therefore, cache management in mixed-critical multi-core systems has become a challenging task. In this paper, we present a dynamic partitioned cache memory for mixed-critical real-time multi-core systems. In this architecture, critical tasks can dynamically allocate and release the cache resourse during the execution interval according to the real-time workload. This dynamic partitioned cache can, on the one hand, provide the predicable cache performance for critical tasks. On the other hand, the released cache can be dynamically used by non-critical tasks to improve their average performance. We demonstrate and prototype our system design on the embedded FPGA platform. Measurements from the prototype clearly demonstrate the benefits of the dynamic partitioned cache for mixed-critical real-time multi-core systems.

Refining and petrochemical processing facilities utilize various process control applications to raise productivity and enhance plant operation. Client–server communication model is used for integrating these highly interacting applications across multiple network layers utilized in distributed control systems. This paper presents an optimum process control environment by merging sequential and regulatory control, advanced regulatory control, multivariable control, unit-based process control, and plant-wide advanced process control into a single collaborative automation platform to ensure optimum operation of processing equipment for achieving maximum yield of all manufacturing facilities. The main control module is replaced by a standard real-time server. The input/output racks are physically and logically decoupled from the controller by converting them into distributed autonomous process interface systems. Real-time data distribution service middleware is used for providing seamless cross-vendor interoperable communication among all process control applications and distributed autonomous process interface systems. Detailed performance analysis was conducted to evaluate the average communication latency and aggregate messaging capacity among process control applications and distributed autonomous process interface systems. The overall performance results confirm the viability of the new proposal as the basis for designing an optimal collaborative automation platform to handle all process control applications. It also does not impose any inherent limit on the aggregate data messaging capacity, making it suitable for scalable automation platforms.

High input voltage, multiple low voltage outputs and high working temperature are the main design challenges for magnetic levitation (maglev) control power supply. The traditional solutions have several problems, such as the uncontrolled duty ratio, the poor cross-regulation capability and low reliability. In order to solve these problems, a quasi-single-stage solution employing the double resonant tank LLC topology is proposed and developed in this paper. The proposed solution can increase significantly the overall conversion efficiency because of the achieved soft-switching over the entire operation range. Moreover, the low input current ripple, high magnetic utilization and high reliability can be achieved. Experimental results of a 210-W laboratory prototype with 220–380V input and four outputs are presented to demonstrate the declared features.

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8V), very low power consumption ($<$0.2nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18$\mu$m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.