Journal of Circuits, Systems and Computers

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

In this study, a new nonlinear and adaptive state feedback controller is proposed for the control of grid connected inverters (GCIs). All the other parameters apart from direct current (DC) bus capacitor are considered uncertain in the design of proposed controller, without disadvantages of singularity and over-parametrization. Three-phase source currents, DC bus voltage and load current are supposed to be available for feedback in the closed loop control system. In this respect, the whole control loop, consisting of DC bus voltage and $d$–$q$ axis current loops, is closed. It is important to highlight that closed loop DC voltage control cannot be achieved by most of nonlinear controllers proposed in literature. In the sense of Lyapunov stability theory, overall control system has the global asymptotic stability. Experimental results demonstrate that the proposed controller guarantees to asymptotically drive tracking errors to zero despite all parameter and external disturbance uncertainties. Results also verify that the proposed controller shows high performance and feasibility.

For a fully digital control of PWM converters, considerable research has been done based on the predictive current control (PCC) scheme. However, it requires a large amount of calculation in the step of experimental implementation. Besides, when compared with the classical linear control scheme, the sampling interval of the PCC scheme must be shorter to obtain the same control performance for current. Due to this, a digital signal processor with excellent performance is required. This paper proposes an improved simplified model PCC scheme for three-phase PWM converters. The main objective is to simplify the PCC scheme. Also, the proposed control scheme is able to reduce the calculation time without affecting the performance. Simulations and experiments are carried out to investigate the presented novel predictive current control scheme. The results indicate that the three-phase PWM converter has excellent static and dynamic performance with the proposed scheme. Besides, the calculation time can be obviously shortened.

In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8V by using Silvaco’s EDA tools. All generated cells have same cell height of 1.58 $\mu$m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS’85 benchmark circuits 74181 and c17 are designed and verified with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.

Wireless transmission compliant to IEEE 802.15.4 standard can be significantly affected by background noise, multipath fading and interference from other radio sources. The influence of such disturbances is most commonly expressed in a form of error probability statistics. Accurate analytical error probability model is hard to acquire, since IEEE 802.15.4 standard uses imperfect spreading sequences. Some prior works in this field tend to idealize these imperfect spreading sequences in order to simplify calculations for error probability parameters. This paper presents an analytical error probability model for IEEE 802.15.4 communication in Rician fading channel, which uses original imperfect spreading sequences without their idealization. Proposed error probability model consists of mutually dependent chip, symbol, bit and packet error probability models. Presented theoretical results are confirmed by independent numerical simulation of IEEE 802.15.4 transmission through Rician fading channel according to the Monte Carlo method.

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC–DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35$\mu$m BCDMOS 2P3M process, and the total size is 1.1$\times$ 1.2mm². The input range and output range of the converter are 6–30 V, and ($V_{\mathrm{\text{input}}}$–3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system.

Automotive communication systems are complex distributed systems. The design of the electrical physical layer (EPL) is a challenging task. Many parameters affect the signal integrity on the analog bus and the combination of parameter variations can lead to effects (e.g., signal reflections) which degrade the signal and compromise the system reliability. Model-based simulations have been widely proposed as the solution for the design, testing and verification of FlexRay networks. This paper proposes a model-based framework for the design and evaluation of FlexRay communication systems. The framework includes the development of FlexRay system components, the design of different network topologies and the simulation and analysis of EPL. The proposed framework has been developed and possible applications have been figured out. Furthermore, the validation of the proposed approach has been addressed. The validation focuses on the accuracy of the simulations in representing the analog signal on the bus, as well as the accuracy in representing the network timing characteristics. The validation exhaustively explores the system design space, achieving a rigorous analysis of the approach reliability: simulations of 40 different network topologies and 1,264 frames have been evaluated, by comparing simulation results with hardware measurements. The results demonstrate that the proposed framework accurately represents the hardware behavior, and it can be an useful toll during the design and early verification of FlexRay communication networks. Due to the lack of a formal validation approach for the validation of the electrical physical layer, the validation is valuable for the FlexRay community.

Many shares are generated from the secret images that are illogical containing certain message within them in visual cryptography. When all shares are piled jointly, they tend to expose the secret of the image. The multiple shares are used to transfer the secret image by using the encryption and decryption process by means of the elliptic curve cryptography (ECC) technique. In ECC method, the public key is randomly generated in the encryption process and decryption process, the private key ($H$) is generated by utilizing the optimization technique and for evaluating the performance of the optimization by using the peak signal to noise ratio (PSNR). From the test results, the PSNR has been exposed to be 65.73057, also the mean square error (MSE) value is 0.017367 and the correlation coefficient (CC) is 1 for the decrypted image without any distortion of the original image and the optimal PSNR value is attained using the cuckoo search (CS) algorithm when compared with the existing works.

Researchers have explored both volatile memories (e.g., SRAM and embedded DRAM) and nonvolatile memories (NVMs, such as resistive RAM) for design of on-chip caches. However, both volatile and nonvolatile memories present unique reliability challenges. NVMs are immune to radiation-induced soft errors, however, due to their limited write endurance, they are vulnerable to hard errors under nonuniform write distribution. By contrast, SRAM has high write endurance but is susceptible to soft errors due to cosmic radiation. SRAM–NVM hybrid caches and the management techniques for them aim to bring the best of SRAM and NVM together, however, the reliability implications of them have not been well understood. In this paper, we show that there are inherent tradeoffs in improving resilience to hard and soft errors in hybrid caches such that mitigating one may result in aggravating another. We confirm this by experiments with two recent hybrid cache management techniques. We also re-examine cache design trends in modern processors from reliability perspective. This paper provides valuable insights to system developers for making reliability-aware design decisions.

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time $T_{\mathrm{\text{dis}}}$ of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time $T_{\mathrm{\text{dis}}}$. Finally, a chip has been fabricated in 0.6$\mu$m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

This paper is aimed to report the consequences in the use of the well-known bootstrap technique in single-phase current-fed full-bridge resonant inverters (SPCFFBRIs) operating with and without reactive energy. Based on both simulations (using the PSPICE${}^{\circledR }$ software) and experiments it is shown that this technique is not feasible for this type of inverters when the load is predominantly reactive. The bootstrap technique conveniently operates when the load is purely resistive or resonant. The unfeasibility in the use of the bootstrap technique with reactive or nonresonant loads comes from the fact that the load voltage is applied to the bootstrap capacitor and, consequently, to the gate of the floating MOSFET, producing an imminent damage both in the control circuit and in the floating MOSFET. Therefore, other alternatives for feeding the floated MOSFETs must be considered.

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

Feature selection has become a key step of fault detection. Unfortunately, the class imbalance in the modern semiconductor industry makes feature selection quite challenging. This paper analyzes the challenges and indicates the limitations of the traditional supervised and unsupervised feature selection methods. To cope with the limitations, a new feature selection method named imbalanced support vector data description-radius-recursive feature selection (ISVDD-radius-RFE) is proposed. When selecting features, the ISVDD-radius-RFE has three advantages: (1) ISVDD-radius-RFE is designed to find the most representative feature by finding the real shape of normal samples. (2) ISVDD-radius-RFE can represent the real shape of normal samples more correctly by introducing the discriminant information from fault samples. (3) ISVDD-radius-RFE is optimized for fault detection where the imbalance data is common. The kernel ISVDD-radius-RFE is also described in this paper. The proposed method is demonstrated through its application in the banana set and SECOM dataset. The experimental results confirm ISVDD-radius-RFE and kernel ISVDD-radius-RFE improve the performance of fault detection.

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

In this paper, a multipath fading compensator(MFC) has been introduced and demonstrated to reduce the signal distortion which arose due to Doppler effect, multipath propagation and self-interference for a multichannel uncoordinated code hopping direct sequence spread spectrum (UCH-DSSS) signaling in underwater communication. The bit error rate (BER) performance analysis of the proposed system obtained both analytically and using P-Spice circuit simulation model with and without jamming signal is presented. It is observed that the BER is independent of the frequencies (used in focused acoustic field (FAF) experiments FAF-06 and FAF-05) and is also less than those of the previous works. Oscilloscope traces indicate that the experimental waveform of the proposed four-channel UCH-DSSS transceiver is almost close to those obtained using P-Spice circuit simulation. The experimental values of BER measured by BER meter also matched well with the BER obtained theoretically. Noise margin and distortion performance also are analyzed from the eye pattern which shows that noise margin and distortion also are independent of frequencies (used in both FAF-06 and FAF-05) and the bandwidth of operation of FAF-06 is $\sim$5.5 times more than that of FAF-05.

Electrical stimulations can promote cell growth, but most electrical stimulators could only output either voltage signals or current signals and do not output arbitrary waveforms according to need. In this paper, a wireless stimulator with adjustable stimulation signals is developed for cell culture. The original waveforms are produced by signal generating circuits. Then under the adjustment of amplification circuits, the original waveforms are converted into current stimulation signals or voltage stimulation signals. Finally, stimulation signals apply onto cells under the monitor of current measuring circuits. The stimulator can provide signals with the following characteristics: (a) required arbitrary waveforms at frequencies ranging from 0 Hz to 100kHz; (b) voltage signals at an amplitude ranging from $-$15V to 15V with a resolution of 1mV; and (c) current signals at an amplitude ranging from $-$1mA to 1mA with a resolution of 1$\mu$A when load resistance is less than 50.0k$\mathrm{\Omega }$. Results of these experiments confirm that the developed instrument can provide adjustable stimulation signals for cell growth.

This paper presents a bandgap reference (BGR) with the characteristics of curvature-compensation and high power supply rejection ratio (PSRR). To achieve a better performance, the base current of BJT is injected to a small segment of resistor string to flatten the temperature variation, and a pre-regulator of the power supply is implemented to improve the PSRR. The circuits, designed in 0.18$\mu$m BCD technology, exhibit an average voltage of 1.212V with temperature coefficient of 2.0ppm/${}^{\circ }\text{C}$ in the range from $-40^{\circ }\text{C}$ to 110${}^{\circ }\text{C}$ at typical condition, and a power supply rejection ratio of $-175.7$dB at low frequency. After 4-bit trimming, Monte Carlo simulation results show that the proposed design gets an accuracy of 0.29%, with a variation of $\pm 3.5$mV. The active design area is 160$\mu \mathrm{\text{m}}\times 206\mu$m, and the power supply current is about 8.2$\mu$A.