Journal of Circuits, Systems and Computers

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009$\mu {\mathrm{\text{m}}}^2$, a worst case delay of 858ps, and a power consumption of 898uW at 1G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600$\mu {\mathrm{\text{m}}}^2$) of the total comparator area and contributes 54% (484$\mu$W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modifications result in 20% and 36% reduction in power consumption and energy delay product (EDP), respectively.

We show a mixer circuit that exhibits infinitely high third-order intercept point (IP3) over a range of RF input levels. It follows from this fact that IP3 is not adequate for characterizing mixers. The formula for calculating IP3 from fundamental- and third-order intermodulation products at a single RF input level is not valid for the mentioned mixer over an RF input power range. Instead of IP3, we suggest a replacement.

In this paper, a new basic 15-level inverter is proposed. By developing the proposed basic unit, a 71-level inverter and generally an $m$-level inverter are proposed. Then, the proposed multilevel inverter is compared with several conventional multilevel inverters in design of minimum 15 levels and 71 levels at the output. By comparing these inverters, it is obtained that the proposed inverter is able to generate higher number of output levels by using lower number of DC voltage sources and power electronic devices that lead to decreased complexity, installation space and total cost of the inverter. Finally, the correct performance of the proposed inverter is reconfirmed through the simulation and experimental results of a 15-level inverter.

In this paper, a new synthesis method for Boolean irreversible functions has been proposed which is based on rotation quantum operators. The primary motivation is that the implementation of these operators is commonly available in quantum technologies. We introduce an approach for synthesizing Boolean irreversible functions in quantum logic which is based on quantum rotation and CNOT operators and uses a prespecified fixed design where by changing the rotation angles a new functionality can be achieved. So this design can be viewed as a programmable array of rotation gates. If reduction in quantum cost is desired, after this step the optimization approach may be applied to reduce the number of gates by using some rules, which leads to a reduction of up to 48% in the quantum cost after optimization compared to the original nonoptimized design obtained from the synthesis method. The paper also introduces efficient designs with rotation operators for some important gates in the quantum circuit libraries. Our main contribution is introducing a novel and low complexity approach for synthesizing irreversible functions using elementary rotation operators with a regular fixed design. Also having as many functions as desired with the same inputs, the execution time just increases by one for each additional function and the circuit width is increased by one for each additional function. It is proved that our approach can always be applied to each Boolean function. We show the correctness of our approach and make an upper bound of the quantum cost of the circuit.

Conventional combinational circuits are generally acyclic (feed-forward) but these circuits can have feedbacks (cycles) which will give more minimized expressions as compared to conventional combinational circuits. Deliberate incorporation of such cycles or feedbacks in conventional combinational circuits eventually results in reduction in number of literals in the expression of the combinational circuits. The reduction in literal counts decreases the number of gates required to implement the expressions of the combinational circuits. Hence, the decrease in number of gates leads to reduction in transistor counts or layout area for the circuits. A cyclic combinational circuit (CCC) is defined as the circuit whose output depends on present inputs only, but at the same time contains one or more feedbacks (cycles). This paper presents a simplified methodology for introduction of cycles (feedbacks) and finding expressions for the CCC. The methodology is applied on LGSynth93 benchmark circuits and a reduction up to 28% in literal counts for expressions of CCC was found which is higher than the reduction achieved by other methodologies. Further the methodology is applied to implement binary comparator which has got three multiple outputs using cyclic combinational technique. The circuits are verified through simulation in cadence virtuoso tools using 45nm technology. Based on simulation results, performance parameters like power consumption, propagation delay and layout area of CCC are compared with the conventional circuits.

In this paper, two new second-order voltage-mode universal filters are proposed. Both of the proposed filters use only two differential voltage current conveyors (DVCCs), four resistors and two grounded capacitors which are advantageous from integrated circuit technology point of view. They can simultaneously provide second-order low-pass, high-pass, band-pass, notch and all-pass responses. They offer orthogonal control of angular resonance frequency and quality factor. However, they have a single matching condition for only all-pass responses. A number of simulations based on SPICE program are accomplished in order to demonstrate the performance of both filters.

A digitally controlled operational amplifier (op-amp) with level-crossing-based approximation is proposed. A high gain is effectively obtained by means of a damping control without a stability problem occurring in the multiple gain stages. Compared to the previous version of the zero-crossing-based algorithmic approximation, the proposed scheme further improves the settling time with the class AB operation obtained by switching of multiple driving paths. For verification, the designed op-amp is applied to a 10-bit pipeline ADC and implemented in a 0.18$\mu$m CMOS technology. Measured results show that the designed op-amp successfully operates at 10-bit resolution, 10MSample/s pipeline ADC and achieves an effective gain of more than 60dB.

This paper mainly discusses the order-frequency characteristics of a promising circuit element: fractor. The concept of fractance, as the fractional-order impedance of a fractor, arose following the successful synthesis of a fractional differentiator or integrator in an analog circuit. In this paper, we studied some electrical properties of a fractor. In particular, the order-frequency characteristics of a fractor are introduced. First, the order-sensitivity characteristics of a fractor are proposed. Second, the order-frequency characteristics of a fractor are studied. Third, the time constant of a fractor is analyzed. Last, through mathematical analysis and simulation results, we discussed in detail some issues of the electrical properties of a fractor, especially its time constant.

Multilevel inverter (MLI) is gaining rapid popularity in high/medium power applications due to low THD and high quality output waveform. Recently, the MLI topologies with reduced part count has attracted the researchers by offering higher number of output voltage level with reduced part count as compared to classical topologies (CHB, NPC and FC). It is observed that these recently proposed topologies are aimed to increase the output level with less number of components but the discussion over their suitability for a particular application is not yet explored completely. The main purpose of this paper is to provide an instructive review and analysis of existing MLIs with reduced part count. An exhaustive comparison of MLIs are assessed based on the number of switches, standing/blocking voltage across the switches, conduction losses, switching losses and cost. With the outcome of comparison results, suitable structure of MLI can be judged with reduced number of components and losses for given applications.

In order to explore the properties depending only on structure such as structural controllability, the structured matrix (SM), and the rational function matrix (RFM) in multi-parameters (RFM) were used to describe the coefficient matrices of systems and networks. In this paper, Definitions 3.3 and 3.4 are given. On the basis of RLCM passive networks, some properties (separability, reducibility, and controllability) of a class of RLCM active networks over $F(z)$ are studied. Some criteria are obtained. Since these criteria depend only on network structures, their applications are straightforward. Finally, two illustrative examples are given.

This paper proposes an 8-bit LC tuned digitally-controlled oscillator (DCO) that exploits a new tunable active inductor (TAI) with a high $Q$-factor. This TAI achieves a maximum $Q$-factor value of 98 over a frequency range of 1770MHz. It tunes from 3.55nH to 15.2nH. The proposed TAI is used in the resonator of a wide tunable low-phase-noise DCO-LC oscillator. The tuning circuitry of the DCO with an additional resistance contributes to better effective capacitance characteristics as compared to the basic topology. Thanks to the capacitive degeneration network formed by a resistance connected in parallel with a capacity, the achieved frequency resolution is between 3kHz and 16kHz without any dithering. The proposed DCO with capacitive degeneration oscillates at a frequency that can be tuned from 1.22 to 3.52GHz with 65% tuning range. It consumes 5.2-mA current from a 1.0-V voltage supply, achieves a phase noise of $-$105.8dBc/Hz at 1-MHz offset and exhibits a figure of merit (FoM) of $-$178dBc/Hz. The proposed digitally-controlled oscillator was implemented in TSMC 90-nm CMOS MS/RF technology.

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

The VHDL design and Field Programmable Gate Array (FPGA) implementation of a fuzzy control system to control the blood glucose level continuously based on current and previous values are presented. The design is based on simple models of the dynamic behavior of the glucose insulin system suitable for real-time control. The system is successfully implemented on FPGA promising efficient hardware implementation to be included in a low power, robust and reliable closed loop health monitoring system.

This paper proposes a novel wideband 90${}^{\circ }$ phase shifter, which comprises a radial stub, a uniform transmission line, and a weak coupled-line (coupling coefficient $\mathrm{\text{C}}\ge 12.7$ dB). The circuit configuration and theoretical analysis equations of the phase shifter are presented. Results demonstrate that the bandwidth (BW) with acceptable phase deviation can be obviously improved by increasing the spanning angle of the radial-stub and the coupling strength of the coupled-line. For return loss better than 10 dB, insertion loss less than 1.05 dB, and phase deviation of $\pm$ 8.5${}^{\circ }$, the fabricated microstrip single-layer phase shifter exhibits BW of 118% from 0.65 GHz to 2.51 GHz. Compared with existing structures, the proposed phase shifter not only has the largest BW but also features simple structure, low-cost, convenient installation, and good portability.

With the need for fast and low-power radiation-hardened processors, advanced technology process is applied to obtain both high performance as well as high reliability. However, scaling down of the size of the transistor makes the transistor sensitive to outside disturbances, such as soft error introduced by the strikes of the cosmic neutron beams. Besides aerospace applications, such reliability should also be taken into consideration for the sub-100nm CMOS designs to ensure the robustness of the circuit. In such circumstances, several radiation-hardened flip-flops are designed and simulated under SMIC 40nm process. Simulation results show that with five aspects (performance, power, area, PVT variation and reliability) taken into consideration, TSPC-based DICE and TMR combined architecture has the best soft-error robustness in comparison with other radiation-hardened flip-flops, and the critical charge of such architecture is 490fC, which is 12.5X higher than the traditional unhardened flip-flop.

A high efficiency self-powered rectifier for piezoelectric (PE) energy harvesting systems is proposed. The rectifier in this paper increases the harvested power from the PE transducer by using two switches to reset the transducer capacitor when appropriate. The control circuit for the proposed rectifier is simple and does not require an external supply voltage. Furthermore, the passive diode of the conventional full-bridge (FB) rectifier is replaced by active diode to reduce the voltage drop along the conduction path and thereby increases the power extraction and conversion capability. Based on SMIC 0.18$\mu$m standard CMOS technology, the simulation results show the voltage conversion efficiency can reach up to 98.9% and the maximum power efficiency is 93.1% when the input current source $I_P=100\mu$A in parallel with internal capacitor $C_P=25$nF and internal resistor $R_P=1$M$\mathrm{\Omega }$.