Journal of Circuits, Systems and Computers

This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance ($g_{mb}$). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42dB to 70.4dB. It has provided 9.24kHz gain bandwidth (GBW), consuming 64nW of quiescent power from a 0.51V single power supply at 15pF load. The proposed OTA in unity gain configuration has ensured reduced total harmonic distortion (THD) of $-52.4$dB at 200Hz frequency and 1V${}_{\mathrm{\text{p-p}}}$ signal swing. Its fully differential class AB input and output structures have ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise. The Cadence Virtuoso environment using GPDK 180nm standard $n$-well CMOS process technology has been used to simulate the proposed circuit.

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence${}^{\circledR }$ Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply.

Mismatch and parasitic effects of bridge capacitors in successive-approximation-register analog-to-digital converter’s (SAR-ADC) split capacitor digital-to-analog conversion (DAC) cause a significant performance deterioration. This paper presents a nonlinearity analysis based on an analytical model, and a modified calibration method utilizing a pre-bias bridge capacitor is accordingly proposed. The proposed method, which uses three-segment split capacitor DAC structure, can effectively eliminate over-calibration error caused by conventional structure. To verify the technique, a 14-bit SAR-ADC has been designed in 0.35-$\mu$m 2P4M CMOS process with the PIP capacitor, and the simulation results show the method can further improve ADC performance.

The energy efficiency in wireless sensor networks (WSNs) is a fundamental challenge. Cluster-based routing is an energy saving method in this type of networks. This paper presents an energy-efficient clustering algorithm based on fuzzy c-means algorithm and genetic fuzzy system (ECAFG). By using FCM algorithm, the clusters are formed, and then cluster heads (CHs) are selected utilizing GFS. The formed clusters will be remaining static but CHs are selected at the beginning of each round. FCM algorithm forms balanced clusters and distributes the consumed energy among them. Using static clusters also reduces the data overhead and consequently the energy consumption. In GFS, nodes energy, the distance from nodes to the base station and the distance from each node to its corresponding cluster center are considered as determining factors in CHs selection. Then, genetic algorithm is also used to obtain fuzzy if–then rules of GFS. Consequently, the system performance is improved and appropriate CHs can be selected, hence energy dissipation is reduced. The simulation results show that ECAFG, compared with the existing methods, significantly reduces the energy consumption of the sensor nodes, and prolongs the network lifetime.

Instantaneous observability is used to watch a system output with very fast signals as well as it is a system property that enables to estimate system internal states. This property depends on the pair of discrete matrices $\{\mathbf{\text{A}}(k),\mathbf{\text{C}}(k)\}$ and it considers that the system state equations are known. The problem is that the system states are inside and they are not always accessible directly. A process, which is a time-varying running program in four parts composes the system under investigation here. It is shown it is possible to apply Kalman filtering on a digital personal computer’s system with particularly the four parts like the ones under investigation. A computing process is performed during a period of time called latency. The calculation of latency considers it as a random variable with Gaussian distribution. The potential application of the results attained is the forecasting of data traffic-jam on a digital personal computer, which has very fast signals inside. In a broader perspective, this method to calculate latency can be applied on other digital personal computer processes such as processes on random access memory. It is also possible to apply this method on local area networks and mainframes.

In recent years, model order reduction (MOR) of interconnect system has become an important technique to reduce the computation complexity and improve the verification efficiency in the nanometer VLSI design. The Krylov subspaces techniques in existing MOR methods are efficient, and have become the methods of choice for generating small-scale macro-models of the large-scale multi-port RCL networks that arise in VLSI interconnect analysis. Although the Krylov subspace projection-based MOR methods have been widely studied over the past decade in the electrical computer-aided design community, all of them do not provide a best optimal solution in a given order. In this paper, a minimum norm least-squares solution for MOR by Krylov subspace methods is proposed. The method is based on generalized inverse (or pseudo-inverse) theory. This enables a new criterion for MOR-based Krylov subspace projection methods. Two numerical examples are used to test the PRIMA method based on the method proposed in this paper as a standard model.

A circuit for adiabatically charging and discharging a supercapacitor was designed. A microprocessor sets the duty ratio of the switching transistors that control the inductor current. Changing the duty ratio in a stepwise fashion causes the output voltage to change in a similar fashion. Stepwise voltage changes enable adiabatic charging and discharging. Current measurements showed that the eight-step charging and discharging of a supercapacitor reduced the energy dissipation to one-eighth of that for a constant-voltage process. The circuit enables precise voltage control in small steps.

In fact, the noise signal is an important problem in signal, circuits and systems. The minimum mean square error (MMSE) estimation technique is useful in several additive white Gaussian noise (AWGN) reduction methods. Original form of MMSE estimator is the integral form. Unfortunately, integral form of MMSE estimator cannot be obtained in simple form for any interesting peaked, heavy-tailed densities (also known as super-Gaussian densities). In this work, we proposed a differential form of bivariate MMSE estimator. The development depends on bivariate Taylor series. The proposed estimator requires no integration. In fact, the derivation is an extension of the existing results for differential form of univariate MMSE estimator.

Due to process scaling, variability in process, voltage, and temperature (PVT) parameters leads to a significant parametric yield loss, and thus impacts the optimization for circuit designs seriously. Previous parametric yield optimization algorithms are limited to optimizing either power yield or timing yield separately, without combining them together for simultaneous optimization. However, neglecting the negative correlation between the performance metrics, such as power and timing measurements, will bring on significant accuracy loss. This paper suggests an efficient multi-objective optimization framework based on Bayes’ theorem, Markov chain method, and an NSGA-II-based genetic algorithm. In the proposed framework, power and timing yields are considered as the optimization objectives to be optimized simultaneously, in order to maintain the negative correlation between power and timing metrics. First, the framework explicitly expresses both leakage current and gate delay in terms of the underlying PVT parameter variations. Then, parametric yields for both metrics are predicted by the computation of cumulative distribution function (CDF) based on Bayes’ theorem and Markov chain method. Finally, a NSGA-II-based genetic algorithm is suggested to solve power–timing optimization problem and generate well-distributed Pareto solutions. Experimental results demonstrate that the proposed multi-objective optimization procedure is able to provide the designer with guaranteed trade-off information between power and timing yields and give them the flexibility in choosing the most appropriate solution(s).

This paper presents the complementary metal oxide semiconductor (CMOS) implementation of active building block, namely, current inverting differential input transconductance amplifier (CIDITA) along with its performance parameters. The detailed study of the proposed CMOS CIDITA has been incorporated. The presented study shows the good performance of CIDITA in terms of good bandwidth range, good linear range of input current, high accuracy and low operating voltage. A new circuit of single active element-based quadrature oscillator is further realized to explore the workability of CIDITA. The proposed circuit of quadrature oscillator employs two grounded capacitors, one resistor and single CIDITA. The proposed quadrature oscillator provides both quadrature current outputs and quadrature voltage outputs simultaneously. The frequency of oscillation of the proposed quadrature oscillator is electronically controllable. The possible practical realization of the CIDITA using commercially available ICs is also given. HSPICE simulation results using 0.18$\mu$m CMOS parameters are given to validate the proposed theory.

In this study, a fifth-order lowpass log-domain Butterworth filter, which is appropriate for Bluetooth/Wi-Fi receiver, is designed with signal flow graph approach. The filter is realized by using a unique translinear integrator circuit. Bluetooth and Wi-Fi modes are obtained without changing the circuit configuration. To change the mode of the filter, it is needed to change the cutoff frequency of the filter that can be electronically tuned by adjusting the external currents. Wi-Fi and Bluetooth receivers have 6MHz and 600kHz cutoff frequencies, respectively. Only BJTs and grounded capacitors were utilized to achieve the desired circuit. Lowpass log-domain Butterworth filter was simulated by using SPICE simulation program. A validated BJT and idealized BJT models are used to obtain simulation results confirming the theoretical analysis.

In this paper, a new structure of nonisolated boost DC–DC converters is proposed. The operation of the proposed structure in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is presented. Then, the critical inductance relation between CCM and DCM is obtained. The voltage gain and current stress of switches are calculated. Finally, the validity of the presented theoretical issues is reconfirmed by using simulation results obtained from PSCAD/EMTDC software.

The aim of this paper is proposing an alternative method to Gorski-Popiel Technique in realization of synthetic transformers. A new synthetic floating transformer (FT) circuit is also given. The proposed synthetic transformer circuit uses two current backward transconductance amplifiers (CBTAs), three resistors, and two grounded capacitors. The primary self-inductance, the secondary self-inductance, and the mutual inductance can be independently controlled and can be tuned electronically by changing the biasing current of the employed CBTAs. It has a good sensitivity performance with respect to tracking errors. A band-pass filter is also realized to test the performance of the proposed synthetic transformer circuit. The validity of the proposed synthetic transformer circuit is demonstrated by PSPICE simulations and experimental results.

A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118$\mu$W, with a delay of 606 ps, with an area of 33.1$\mu$m², resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage $V_{\mathrm{\text{DD}}}=1.2$V, input signal frequency $f_{\mathrm{\text{in}}}=200$MHz is used. This 1-bit FA is designed and implemented using Cadences' 90nm “generic-process-design-kit” (GPDK).

Artificial neural networks (ANNs) are implemented in hardware when software implementations are inadequate in terms of performance. Implementing an ANN as hardware without using design automation tools is a time consuming process. On the other hand, this process can be automated using pre-designed neurons. Thus, in this work, several artificial neural cells were designed and implemented to form a library of neurons for rapid realization of ANNs on FPGA-based embedded systems. The library contains a total of 60 different neurons, two-, four- and six-input biased and non-biased, with each having 10 different activation functions. The neurons are highly pipelined and were designed to be connected to each other like Lego pieces. Chip statistics of the neurons showed that depending on the type of the neuron, about 25 selected neurons can be fit in to the smallest Virtex-6 chip and an ANN formed using the neurons can be clocked up to 576.89MHz. ANN based Rössler system was constructed to show the effectiveness of using neurons in rapid realization of ANNs on embedded systems. Our experiments with the neurons showed that using these neurons, ANNs can rapidly be implemented as hardware and design time can significantly be reduced.

Integration of safety-critical tasks with different certification requirements onto a common hardware platform has become a growing tendency in the design of real-time and embedded systems. In the past decade, great efforts have been made to develop techniques for handling uncertainties in task worst-case execution time, quality-of-service, and schedulability of mixed-criticality systems. However, few works take fault-tolerance as a design requirement. In this paper, we address the scheduling of fault-tolerant mixed-criticality systems to ensure the safety of tasks at different levels of criticalities in the presence of transient faults. We adopt task re-execution as the fault-tolerant technique. Extensive simulations were performed to validate the effectiveness of our algorithm. Simulation results show that our algorithm results in up to $15.8\%$ and $94.4\%$ improvement in system reliability and schedule feasibility as compared to existing techniques, which contributes to a more safe system.

Recently, a series of typical three-dimensional dissipative chaotic flows where all but one of the nonlinearities are quadratic are studied. Based on this research, a novel chaotic model with only one single linearity is proposed by introducing cubic terms and four new chaotic systems with various characteristics are found. Besides, a chaotic family with a single linearity is constructed with those four chaotic systems and 12 existing systems SL₁–SL${}_{12}$ of the chaotic flows. Exploiting the new systems, basic dynamic behaviors are analyzed, including the strange attractors, equilibrium points, Lyapunov exponents as well as the property of multistability. In addition, the corresponding simulation results are illustrated to show those properties expressly. In realizing the chaotic circuit, we utilize the field programmable gate array (FPGA), which is of considerable flexibility, good programmability and stability, instead of analog devices that are easily affected by surroundings. More importantly, the circuit of the proposed chaotic family is realized on a single FPGA over register transfer level (RTL) using 32-bit fixed-point operation. Finally, an experimental FPGA-based circuit is constructed, and the output results are shown on oscilloscope, which agree well with the numerical simulations.

Data converters play a key role in modern analog/mixed-signal systems. Accordingly, it is important to investigate their performance and yield under uncertain parameters over the design process. An efficient approach for automatic design and yield enhancement of data converters is presented. The proposed algorithm generates a general netlist for each data converter and improves transistor sizing to reach acceptable values for performance parameters with an evolutionary process, and finds the best yield simultaneously. The applied framework on two data converter structures demonstrates a reliable circuit with optimum performance, power consumption, and area overhead over a single evolutionary process in 0.18$\mu$m technology.