Journal of Circuits, Systems and Computers

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decoding ability as the number of free variables is limited by the test access mechanism bandwidth. We have found that even within this limitation, it is possible to improve the decodability by creating fast and wide-spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we proposed a decompressor combining a XOR network and a linear feedback shift register (LFSR)-like automaton; we place the XOR network on the LFSR inputs. We demonstrate that due to this arrangement, the combined decompressor can be used without any phase shifter or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

Nowadays, power is a dominant factor that constrains highly integrated hardware-systems designs. The implied problems of high power density, causing chip overheating, or limited power source in modern Internet-of-Things devices are most commonly dealt with the use of the dynamic power management. This method enables to use power-reduction techniques, such as clock gating, power gating, or voltage and frequency scaling. Since the adoption of power management is quite difficult in modern complex systems, there are new approaches evolving intended to simplify power-constrained systems design. We have also proposed such an approach, utilizing the system level of design abstraction and increased automation in the design process. In this paper, the proposed hybrid verification approach is described that represents an integral part of the suggested design methodology. It consists of formal and informal techniques, enabling the verification process to begin at the very early specification stage of the system development. Our approach helps a designer to create correct and consistent power-management specification and verifies whether the specified power intent is preserved after design refinement. The continuous automated verification steps can quickly find errors at early design stages and thus reduce the amount of design re-spins, which speeds-up the overall development process.

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

High power consumption is a key factor hindering system-on-chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on intellectual property (IP) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing an estimation methodology that fits IP cores power modeling needs. The main contribution of this paper is the development and validation of a hybrid power estimation technique (HPET), in which information coming from different abstraction levels is used to assess the power consumption in a fast and accurate manner. HPET is based on an effective characterization methodology of the technology library and an efficient hybrid power modeling approach. Experimental results, derived using HPET, have been validated on different benchmark circuits synthesized using the 28nm “fully depleted silicon on insulator” (FDSOI) technology. Experimental results show that in average we can achieve up to 68$\times$ improvement in power estimation run-time while having transistor-level accuracy. For both analyzed power types (instantaneous and average), HPET results are well correlated with respect to the ones computed in SPECTRE and Primetime-PX. This demonstrates that HPET is an effective technique to enhance power macro-modeling creation at high abstraction levels.

A novel method of nodal impedance calculation is presented in this paper. This method is capable of time-efficient calculation of arbitrary two-point complex impedance in an analog and mixed-signal circuit and could improve the development time of impedance-based tests both in DC and AC domain. A fault simulation methodology based on the proposed method is described in detail. Several experiments are provided that prove the time efficiency of the method. Experimental application showing the benefits of the method on a real circuit is provided as well.

In state-of-the-art automotive controllers, functional tests are used to check their integrity in the field. Features dedicated to production test of integrated circuits such as scan chains are not applied in the embedded system. However, such test structures enable a more effective and diagnostic test, which improves the fault analysis in case of a system failure and even increases system reliability. To achieve this, an access to the integrated test logic is required. This paper describes a concept of a test access to embedded systems via high-speed standard interfaces. The extended test logic as well as an appropriate test routine is presented.

Structural test is widely adopted to ensure high quality for a given product. The availability of many commercial tools and the use of fault models make it very easy to generate and to evaluate. Despite its efficiency, structural test is also known for the risk of over-testing that may lead to yield loss. This problem is mainly due to the fact that structural test does not take into account the functionality of the circuit under test. On the other hand, functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over- as well as under-testing issues. More in particular, for microprocessor testing, functional test is usually applied by exploiting the Software-Based-Self-Test (SBST) technique. SBST applies a set of functional test programs that are executed by the processor to achieve a given fault coverage. SBST fits particularly well for online testing of processor-based systems. In this work, we describe a technique able to execute functional test programs as if they were structural tests. In this way, they can be applied during the end-of-production test in order to achieve good fault coverage and, at the same time, avoiding any over-test problems. We will show that it is possible to map functional test programs into the classical structural test schemes, so that their application simply requires the presence of a scan chain. Finally, we present a compaction algorithm able to significantly reduce the test length. Results carried out on two different microprocessors show the advantages of such approach.

This paper presents an 8-channel neural stimulator application-specific integrated circuit (ASIC) for biphasic stimulation of the visual cortex, fabricated in a 0.35$\mu$m AMS HV process. Each channel is composed of a standard SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120V compliant HV output stage. Thus, it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to $\pm$8.192mA with 32$\mu$A steps. The measured maximum differential nonlinearity (DNL) of the current output does not exceed 1.1 LSB. The on-board current reference provides the output current of 16$\mu$A with a very low temperature variation. The maximum anodic and cathodic current mismatch after calibration is 25$\mu$A. The measured interpulse leakage current does not exceed 60pA. The ASIC was also tested with the electrode–tissue model, which describes the PEDOT electrodes of 560$\mu$m diameter in the phosphate buffer saline (PBS). The measurement results approve the possibility to stimulate with arbitrary current amplitudes with frequencies up to 1.5kHz.

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a defined HI or LO level. In this case the sequential element requires extra time to decide which digital output level to finally present, which is perceived as an output delay. The amount of this delay depends on how close the element’s state is to the balance point, at which the delay may, theoretically, become infinite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its effect. Traditionally this is done by means of a “mean time between upsets” (MTBU) which gives the expected interval between two metastable upsets. The latter is defined as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a definition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely finalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of “failure” but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in different implementations, point out its relation to the traditional MTBU model parameters, namely $\tau$ and $T_0$, and show how to use it for calculating the performance penalty in a value-safe environment.