Journal of Circuits, Systems and Computers

The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO’s output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique.

This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, $-$80dB power supply rejection (PSR) @1kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard $0.18\mu$m CMOS process, consuming 50$\mu$A at 25${}^{\circ }$C with a supply voltage of 3.3V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18ppm/${}^{\circ }$C over the temperature range from $-40^{\circ }$C to 120${}^{\circ }$C. Monte Carlo simulation and Experimental Results validate the design.

Modeling and analysis of a MEMS piezoelectric (PZT-Lead Zirconate Titanate) unimorph cantilever with different substrates are presented in this paper. Stainless steel and Silicon $〈110〉$ are considered as substrate. The design is intended for energy harvesting from ambient vibrations. The cantilever model is based on Euler–Bernoulli beam theory. The generated voltage and power, the current density, resonance frequencies and tip displacement for different geometry (single layer and array structure) have been analyzed using finite element method. Variation of output power and resonant frequency for array structure with array elements connected in parallel have been studied. Strain distribution is studied for external vibrations with different frequencies. The geometry of the piezoelectric layer as well as the substrate has been optimized for maximum power output. The variation of generated power output with frequency and load has also been presented. Finally, several models are introduced and compared with traditional array MEMS energy harvester.

QR decomposition (QRD) is one of the most widely used numerical linear algebra (NLA) kernels in several signal processing applications. Its implementation has a considerable and an important impact on the system performance. As processor architectures continue to gain ground in the high-performance computing world, QRD algorithms have to be redesigned in order to take advantage of the architectural features on these new processors. However, in some processor architectures like very large instruction word (VLIW), compiler efficiency is not enough to make an effective use of available computational resources. This paper presents an efficient and optimized approach to implement Givens QRD in a low-power platform based on VLIW architecture. To overcome the compiler efficiency limits to parallelize the most of Givens arithmetic operations, we propose a low-level instruction scheme that could maximize the parallelism rate and minimize clock cycles. The key contributions of this work are as follows: (i) New parallel and fast version design of Givens algorithm based on the VLIW features (i.e., instruction-level parallelism (ILP) and data-level parallelism (DLP)) including the cache memory properties. (ii) Efficient data management approach to avoid cache misses and memory bank conflicts. Two DSP platforms C6678 and AK2H12 were used as targets for implementation. The introduced parallel QR implementation method achieves, in average, more than 12$\times$ and 6$\times$ speedups over the standard algorithm version and the optimized QR routine implementations, respectively. Compared to the state of the art, the proposed scheme implementation is at least 3.65 and 2.5 times faster than the recent CPU and DSP implementations, respectively.

In this paper, a new second-order current-mode universal filter using only two plus-type differential voltage current conveyors, three resistors and two grounded capacitors is proposed. The proposed circuit with two identical inputs and three outputs can simultaneously provide second-order high output impedance low-pass, band-pass and notch filter responses. Also, it can realize high-pass and all-pass filter responses with interconnection of relevant output currents. It can be easily tuned electronically. It can be operated properly at high frequencies. A number of simulations based on SPICE program and an experimental test are achieved in order to demonstrate the performance of the proposed filter.

Genetic Algorithm (GA) applications in analog design circuits play an important role with promising results. This paper introduces a proposed methodology based on the genetic algorithm and the symbolic representation to generate equivalent op-amp configurations for well-known filters. The proposed methodology is applied to the Tow-Thomas (TT) filter to generate 168 different configurations. Moreover, it is also applied on the KHN filter resulting in 30 equivalent circuits for each type. A part of the generated realizations is tested through simulations using PSPICE simulator and the simulation results determine the number of accepted circuits. A simulation comparison between the original filter configuration and some of the accepted configurations is done. Fortunately, a better performance compared to the original configuration is obtained from some generated circuits.

Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5m W, and 0.06m W, respectively, at 10MHz in a 0.18$\mu$m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50$\mu$W/MHz with 10,800 gates in a 0.18$\mu$m CMOS process.

In this paper, fuzzy logic controller (FLC)-based three-phase shunt active power filter with photovoltaic (PV) system is proposed. This filter comprises voltage source converter (VSC) with DC link capacitor at the input side and is supplied by PV system. The salient feature of the filter is that it provides reactive power compensation with line current harmonic reduction and also neutral compensation at point of common coupling (PCC). The PV system and a battery are connected with VSC through DC–DC converter. This paper also proposes a control algorithm using instantaneous $p$-$q$ theory that generates a reference current to counteract the harmonics. The FLC controls the DC link voltage in reference to the above reference current. The performance of the proposed filter for compensation is confirmed by using the MATLAB/Simulink environment and results are validated.

The paper presents a novel 5.15GHz–5.825GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-$\mu$m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843mm². The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14dB power conversion gain, $-$6dBm input third-order intercept point (IIP3), 6.85dB double side band (DSB) noise figure. The total mixer current is about 1.54mA from 1.4V supply voltage including output buffer. The total dc power consumption is 2.15mW.

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

In this paper, a joint direction of arrival (DOA) and frequency estimation algorithm of narrow-band signals is proposed via compressed sensing (CS) parallel factor (PARAFAC) framework. The proposed algorithm constructs the data model into a PARAFAC model, and compresses it to a smaller one. Then trilinear alternating least-squares (TALS) algorithm is exploited to estimate the compressed parameter matrices, and finally the joint DOA and frequency estimation is obtained via the spatial sparsity and the frequency sparsity. Due to compression, the proposed algorithm has lower computational complexity than the conventional PARAFAC algorithm, and saves more memory capacity for practical application. The DOA and frequency estimation performance of the proposed algorithm is very close to that of the conventional PARAFAC algorithm, and better than those of the estimation of signal parameters via rotational invariance techniques (ESPRIT) algorithm and the propagator method (PM). Furthermore, the proposed algorithm can achieve automatically paired DOA and frequency estimation. Besides, it is applicable for nonuniform linear arrays. Effectiveness of the proposed algorithm is assessed by simulations.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

This paper presents an analysis of the security performance and evaluation of the hardware architecture of the redundant bit security (RBS) cryptosystem. RBS is a lightweight symmetric encryption algorithm that targets resource-constrained RFID devices. Unlike the existing cryptosystems, RBS simultaneously provides confidentiality, authentication, and integrity of the plaintext by inserting hash-generated redundant bits among the already modified plaintext data. A flexible-length hash algorithm in our optimized hardware architecture allows RBS to support different key sizes which allows flexibility in the security level. Our analysis shows the resilience of RBS against powerful and well-known attacks such as differential attacks and known-plaintext attacks. We compare the performance of the RBS cryptosystem against other distinguished ciphers developed for RFID systems. Simulation results show that RBS results in approximately 100%, 239%, and 153% higher hardware efficiencies while requiring 48%, 56%, and 59% less energy-per-bit compared to H-PRESENT, HB-2, and Grain, respectively. Such results present confirmatory evidence that RBS is a superior solution for providing security in resource-constrained systems such as RFID systems especially when authentication is a priority.

This paper investigates the exponential synchronization of chaotic systems with time delays via periodically intermittent control. Under the new differential inequality, some novel synchronization criteria are derived. In contrast to the existing works, the proposed results are less conservative because they can obtain more precise synchronized rate under the identical control conditions and remove the restrictions on the control period (or the control width) and the time delay. By using special parameters, the feasible region D(ξ), which guarantees the response system synchronizes with the drive system with synchronized rate 0.5ξ, is obtained. The Lu chaotic attractor and a first-order chaotic system with time delay are presented to demonstrate the effectiveness of the proposed results.

In this paper, we present a new method increasing quality factor of active filter structure in the literature and a new designed filter. The new method is easily applied to all different filter modes with the proper feedback circuit. The center frequency of the filter remains constant as quality factor of filter increases. Also, quality factor can be also tuned electronically by changing the biasing current of the feedback circuit. Furthermore, the performance of the method is demonstrated by CMOS simulation of differential voltage current conveyor and transconductance amplifier. Quality factor value of the filter can also be easily adjusted electronically between 1 and 20 with the presented method. Finally, an application example of the presented method is presented for double tuned amplifier for intermediate frequency pre-amplifier of FM receiver.

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

Fractional-order filter design examples, realized through the substitution of fractional-order capacitors and inductors by a re-configurable active emulator, are presented in this paper. The implementation of the emulator is achieved using Current Feedback Operational Amplifiers (CFOAs) as active elements with the required fractional-order differentiation/integration performed through the employment of an integer-order multi-feedback topology. An important benefit, from the design flexibility point of view, is that the same topology could be re-configured for emulating both fractional-order capacitors and inductors through the appropriate selection of the time-constants and gain factors. The behavior of the realized filters is experimentally evaluated using commercially available CFOAs.

Transmission power control is the strategy in which a sensor node transmits at a lowest possible power level to maintain an error-free transmission being in dynamic multi-path fading environment, ensuring energy efficiency and interference minimization. In this paper, we propose a novel technique for power control while considering a realistic radio fading environment. The proposed technique is based on Kalman filter that iteratively estimates and predicts the upcoming received radio signal strength indicator (RSSI) values. Theoretical analysis and simulation results are given that show the better performance of the proposed methodology in comparison to existing power control strategies in time-varying fading propagation environment.

Experimental results of a SPICE-compatible macromodel to model the nonlinear behavior of second generation current conveyors (CCIIs) at low frequency are presented. The derived macromodel includes not only those real physical performance parameters more important for CCII like the dynamic range, slew rate, DC gain and gain–bandwidth product, but parasitic resistors and capacitors associated to the input and output terminals are also included. To validate the derived macromodel, a saturated nonlinear function series (SNFS) was built by using AD844AN commercially available active device configured as CCII and embedded in a chaotic system. After that, an experimentally generated chaotic signal was applied as excitation signal to SNFS built with AD844AN foundry-provided macromodel and the proposed herein. Our results indicate that the derived macromodel can be used in the time-domain for forecasting the behavior of nonlinear circuits without worsening the accuracy and at less time compared with the foundry-provided macromodel.

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the $n$-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm² area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.