Journal of Circuits, Systems and Computers

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6V, dropout voltage of 200mV and a quiescent current of 64.4$\mu$A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95mV for a load current changes from 0mA to 100mA and an overshoot of 150.1mV for a current change of 100–0mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6$\mu$V/mA and power supply rejection (PSR) of $-$47.8dB@ 10kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180nm UMC CMOS process is employed.

This paper presents the design and analysis of a polygon-connected autotransformer based 20-pulse AC–DC converter which supplies direct torque-controlled induction motor drives (DTCIMDs) in order to have better power quality conditions at the point of common coupling. The proposed converter output voltage is accomplished via two paralleled 10-pulse AC–DC converters each of them consisting of five-phase diode bridge rectifier. An autotransformer is designed to supply the rectifiers. The design procedure of magnetics is in such a way that makes it suitable for retrofit applications where a six-pulse diode bridge rectifier is being utilized. The proposed structure improves power quality criteria at AC mains and makes them consistent with the IEEE-519 Standard requirements for $\mathrm{\text{SCR}}>20$. Furthermore, near-unity power factor is obtained for a wide range of DTCIMD operations. A comparison is made between six-pulse and proposed converters from the viewpoint of power quality indices. Results show that input current total harmonic distortion (THD) is less than 8% for the proposed topology at variable loads. A laboratory prototype of the proposed polygon-connected autotransformer-based 20-pulse AC–DC converter is developed and test results are presented to validate the developed design procedure and the simulation models of this AC–DC converter under varying loads.

This paper presents a modified pulse width modulation (PWM) readout method for DPS with block-based self-adjusted reference voltage to extend dynamic range (DR). In this scheme, pixel arrays are divided into blocks with the same size, and the exposure process consists of two periods. During the first exposure, block-based reference voltage is generated based on the average photocurrent within the block. In the second exposure, the generated voltage is used as the reference voltage for PWM readout. Then the quantization results are combined together to represent the luminance information. DR and peak signal-to-noise ratio (PSNR) were discussed with different images and integration time. Simulation results show that this scheme can achieve a DR of over 96dB with 8-bit memory and 8-bit ADC and 145dB with 12-bit memory and 12-bit ADC. It also has 28.98dB PSNR on average, better than 20.11dB in fixed reference voltage method and 17.25dB in ramp reference voltage method. Combining the feature of active pixel sensor (APS) and PWM readout, this scheme allows better DR but also obtains less distortion of the image reconstruction.

A compact quenching circuit for Single Photon Avalanche Diode (SPAD) arrays is presented. The proposed circuit preserves the advantages of small area occupation and low power consumption, since it mainly adopts the junction capacitance of the detector to sense the avalanche current. The sensing time is now limited more by the detector rather than the circuit itself. Fabricated in TSMC standard 0.35$\mu$m CMOS process, the proposed circuit only occupies an area of 20$\mu$m$\times$31$\mu$m and can operate properly with the detector biased up to 5V above breakdown. The circuit functionality has been verified by experimental measurements, operating with 64$\times$64 InGaAs/InP single photon avalanche diode arrays for time-of-flight-based applications.

DNA computation is an emerging technology to perform complex information processing at the nanoscale era. Molecular programming with localized DNA hybridization is a systematic, parallel and scalable approach for DNA computation. Considerable methods are developed for the design of Localized DNA circuits. Due to significant theoretical and technological difference between this technology and conventional electronic system, a customized design flow for this technology is a real requirement. We proposed a customized DNA cell placement algorithm for localized DNA hybridization technology in this paper. The main objectives in the proposed placement algorithm are minimizing the die footprint and total signal propagation path. Our implementations and simulations show the feasibility and efficiency of the proposed placement algorithm.

There are many challenges addressed in MRC compression, such as the segmentation of the document into foreground and background layers, represented as a binary mask. Usually, the resulting quality of a MRC compression method depends on the segmentation algorithm used to compute the binary mask. The aim of this work is to leverage state-of-the-art techniques in document segmentation allowing further content, such as text or images, to be exploited in an efficient way. Then, a novel methodology is proposed that leads to increasing document segmentation performance for MRC compression scheme.

A low-cost regulator insensitive to temperature and supply voltage variations for power management units of Radio Frequency Identification (RFID) tag chips and other batteryless devices is proposed in this paper. The commonly used regulator has poor temperature rejection ratio (TRR) and poor voltage rejection ratio (VRR). By using combination resistors and long channel transistors, the bias and regulator circuits are improved over temperature variations. A power supply rejection (PSR) enhancement branch is also added to suppress the supply noise and stabilize the bias current. The regulator is designed and fabricated in the HJTC 0.25$\mu$m CMOS technology. Simulation results show that this regulator achieves 0.044mV/${}^{\circ }$C TRR when temperature varies from $-20^{\circ }$C to 70${}^{\circ }$C and 1.1mV/V VRR while the supply voltage of the regulator ranges from 4 to 12V. The PSR is nearly $-$100dB at DC. The area of this regulator is 0.102mm² including the bias circuit. The measurement results meet simulation results well and this regulator is successfully applied in HF passive tag chips within voltage deviations of $\pm 5\%$ of 2.5V.

By scaling the semiconductor industry to nano-scale era, design and prototyping cost of cell-based Application-Specific Integrated Circuits (ASICs) becomes more expensive and it makes Field Programmable Gate Arrays (FPGAs) more popular among designers. However, there is a gap between FPGAs and ASICs in terms of timing, dynamic power consumption and logic density. Three-dimensional integration, particularly in the full monolithic process, has been considered as a promising solution to reduce the performance gap of ASICs and FPGAs. In this paper, two new architectures for the monolithically integrated 3D-FPGAs are introduced. In order to exploit the great potentials of the suggested architectures, a new three-dimensional FPGA placement algorithm is proposed thereafter. The proposed placement algorithm, named JABE, is the first of its kind that enables designers to take advantages of the large number of vertical interconnections in the monolithically stacked 3D-FPGAs. Our experiments show a 24% timing improvement for the new architectures and CAD algorithms compared with the conventional TSV-based 3D-FPGAs and design flows. In addition, improvements in terms of the total wirelength and area footprint are reported for the proposed placement algorithms and new architectures.

In the present work, reactive power planning problem along with voltage stability margin is addressed by effective co-ordination of reactive power sources. Modal analysis and L-index methods are used to detect weak nodes of the system accordingly. Differential Evolution (DE) and Genetic Algorithm (GA)-based optimization techniques are applied for the proper co-ordination of Var sources under base and increased loading conditions maintaining voltage stability of the connected power network. The problem is multi-objective and IEEE 30 bus system is taken as the standard system. It is observed that modal analysis based detection of weak nodes are more effective than the L-index-based detection. Moreover, the DE-based optimization algorithm gives better result compared to GA-based approach in maximizing reactive power reserves.

In this study a modified learning vector quantization (LVQ) algorithm is proposed. For this purpose, relevance LVQ (RLVQ) algorithm is efficiently combined with a reinforcement mechanism. In this mechanism, it is shown that the proposed algorithm is not affected constantly by both relevance–irrelevance input dimensions and the winning of the same neuron. Hardware design of the proposed scheme is also given to illustrate the performance of the algorithm. The proposed algorithm is compared to the corresponding ones with regard to success rate and running time.

This paper presents design of electronically reconfigurable fractional-order filter that is able to be configured to operate as fractional-order low-pass filter (FLPF) or fractional-order high-pass filter (FHPF). Its slope of attenuation between pass band and stop band, i.e., order of the filter, is electronically adjustable in the range between 1 and 2. Also, pole frequency can be electronically controlled independently with respect to other tuned parameters. Moreover, particular type of approximation can be also controlled electronically. This feature set is available both for FLPF and FHPF-type of response. Presented structure of the filter is based on well-known follow-the-leader feedback (FLF) topology adjusted in our case for utilization with just simple active elements operational transconductance amplifiers (OTAs) and adjustable current amplifiers (ACAs), both providing possibility to control its key parameter electronically. This paper explains how reconfigurable third-order FLF topology is used in order to approximate both FLPF and FHPF in concerned frequency band of interest. Design is supported by PSpice simulations for three particular values of order of the filter (1.25, 1.5, 1.75), for several values of pole frequency and for two particular types of approximation forming the shape of both the magnitude and phase response. Moreover, theoretical presumptions are successfully confirmed by laboratory measurements with prepared prototype based on behavioral modeling.

A simple chaotic system with a single nonquadratic term is developed to be a switchable chaotic signal generator in this paper. Additional nonlinearity of the absolute value function is introduced for reforming the structure without damaging the basic dynamics but yielding a new independent amplitude–frequency controller. A switchable chaotic experimental oscillator is designed afterwards, where two coefficients corresponding to two independent rheostats rescale the amplitude and frequency of the chaotic signals smoothly. To our knowledge, this has never been found in other chaotic oscillators.

The integration of mixed-critical tasks into a platform is an increasingly important trend in the design of real-time systems due to its efficient resource usage. With a growing variety of activation patterns considered in real-time systems, some of them capture arbitrary activation patterns. As a consequence, the existing scheduling approaches in mixed-criticality systems (MCs), which assume the sporadic tasks with implicit deadlines, have sometimes become inapplicable or are ineffective. In this paper, we extend the sporadically activated task model to the arbitrarily activated task model in MCs with the preemptive fixed-task-priority schedule. By using the event arrival curve to model task activations, we present the necessary and sufficient schedulability tests that are based on the well-established results from Real-Time Calculus. We propose to use the busy-window analysis to do the sufficient test because it has been shown to be tighter than the sufficient test of using Real-Time Calculus. According to our experimental results, for sporadic task sets, our proposed test can achieve the same performance as the state-of-the-art schedulability test. However, compared with the previous schedulability analysis of preemptive fixed-task-priority, our approaches can handle more general tasks with blocking, jitter, and arbitrary deadlines.

This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are deduced in terms of the fractional-order parameters. The extra degree of freedom provided by the fractional-order elements increases the design flexibility. Eight special cases including the integer case are illustrated with their numerical discussions. Three different phases are produced with fixed sum of $2\pi$ which can be completely controlled by fractional-order elements. A general design procedure is introduced to design an oscillator with a specific phase and frequency. Two general design cases are discussed based on exploiting the degrees of freedom introduced by the fractional order to obtain the required design. Spice circuit simulations with experimental results for some special cases are presented to validate the theoretical findings.

With the discovery of the memristor devices, most researchers have focused on the simulation and application of memristive characteristics, especially the nonvolatile storage potential of the memristor. However, the fusion of image storage and operation is seldom discussed. Therefore, this paper focuses on the electrical characterization of silver chalcogenide based on memristor devices, which can be used as a synapse to mimic the STDP and SRDP learning rules in neuromorphic systems. Then on this basis, a improved memristive cross array structure is designed, whose storage and operation are set in a single unit. Furthermore, this improved memristive cross array and image processing are combined with adjusting the memristor resistance by synaptic plasticity to achieve the integration of storage and processing. Finally, the effectiveness of the design is verified by the LTSPICE experiments of the nonlinear grayscale transformation and logic operation of the image. The design breaks the gap between the processing and storage in the Von Neumann architecture, which will be helpful to the development of the parallel computing in the future.

A novel envelope modulator for envelope tracking RF power amplifier (PA) is presented in this paper. The proposed modulator consists of a parallel combination of analog class AB and digitally controlled hybrid PAs. The analog and digital class AB PAs are effective in both reducing the clock frequency and also static power dissipation, thus improving the efficiency of the modulator. On the other hand, lower clock frequencies result in simpler and more power-efficient digital to analog converters required in the architecture. The modulator digital block is evaluated with a 45nm CMOS technology. The overall power consumption of the digital block is around 76mW at 800MHz clock frequency. As an application, the designed digital block is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital block power consumption, is around 80.7% at an average 32dBm output power for a 5MHz input signal.

Design, fabrication and measurement of a high-selectivity dual-mode dual-band bandpass filter are presented in this paper. The resonance frequencies of the filter are 1.8GHz and 2.4GHz which are generated by a meander-loop resonator and a square-loop resonator. The two dual-mode single-band-loop resonators are stacked on each other and create a dual-band bandpass filter. Some advantages of our design are compact size, high selectivity, low loss and also no dependence of two bands, resonance frequencies on each other. The measurement results exhibit that the minimum insertion losses are 0.19dB for 1.8GHz and 0.32dB for 2.4GHz. Moreover return losses are better than 43.2dB and 40.6dB for 1.8GHz and 2.4GHz, respectively. The proposed filter has a size of $18\times 18$mm². This microstrip filter is fabricated on RT/Duroid6010 substrate with dielectric constant 10.8 and thickness 1.27mm and its equivalent circuit is also offered. The measured results exhibit good agreement with the simulated ones.

This paper describes a new single-input multiple-output (SIMO) mixed-mode universal biquad $G_m$–$C$ filter. It can realize all kinds of filter responses including high-pass, band-pass, low-pass, band-stop and all-pass filters, simultaneously. Moreover, in this structure, all of these filters in all states of voltage mode, current mode, transresistance mode and transconductance mode are achieved by the same topology without any convertor. The proposed filter employs three operational transconductance amplifiers (OTAs) with four inputs and one output, three fully differential OTAs and two grounded capacitors. In other words, this filter is composed of six $G_m$ blocks and two grounded capacitors. The grounded capacitors are suitable for integrated circuit implementation. In order to reduce the power consumption, the OTAs are biased in subthreshold region. In addition, sensitivity analysis is included to show the low active and passive sensitivity performances of the filter. This filter is designed and simulated in HSPICE with 0.18$\mu$m model CMOS technology parameters. The simulation results show that the filter consumes only 75$\mu$W and operates at 1.5MHz with $\pm$0.5V supply voltages and capacitors $C_1=C_2=2$pF.

In the present paper, the problem of digital implementation of retuning fractional-order (FO) controllers for an unstable plant — a real-life laboratory model of a Magnetic Levitation System (MLS) — is investigated. Retuning control is applied to an existing closed-loop PID control system through the use of a hardware FO controller prototype. An implementation method for the retuning controller is proposed. Three types of hardware-in-the-loop (HIL) experiments are considered. First, the plant is simulated using a suitable dynamic model. Second, the real-life laboratory model of the MLS is controlled. In the third type of experiment, a MATLAB implementation of the retuning controller is evaluated as a benchmark. Three controllers obtained in an earlier work are tested with this setup. Experimental results are compared and discussed.