Journal of Circuits, Systems and Computers

The main constraint that restricts wireless charging technology successfully applied in miniature medical electronic equipment is that the volume of the transmission coil is difficult to reduce. The printed circuit board (PCB) coil can take advantage of multi-layer wiring space to achieve the coil stack, achieving the purpose of increasing the relative magnetic flux, so that it could replace the traditional spiral coil to become the medium of wireless power transmission in the mini-medical electronic device.

In this paper, we analyzed several electrical parameters that could affect the 3D PCB rectangular coil inductance value based on the 3D PCB rectangular coil inductance computing method. Then we sort these influencing factors so that these results can help designers to design the 3D PCB coil. The conclusions are as follows: (1) number of layers, total number of turns have positive correlation with the self-inductance; metal width, substrate thickness, the pitch between adjacent turns have negative correlation with the self-inductance. (2) The sorting of influencing factors of the inductance is as follows: total number of turns$>$number of layers, the pitch between adjacent turns$>$substrate thickness$>$metal width.

We deal with the endurance problem of Phase Change Memories (PCM) by proposing Compression for Endurance in PCM RAM $($CEPRAM$)$, a technique to elongate the lifespan of PCM-based main memory through compression. We introduce a total of three compression schemes based on already existent schemes, but targeting compression for PCM-based systems. We do a two-level evaluation. First, we quantify the performance of the compression, in terms of compressed size, bit-flips and how they are affected by errors. Next, we simulate these parameters in a statistical simulator to study how they affect the endurance of the system. Our simulation results reveal that our technique, which is built on top of Error Correcting Pointers (ECP) but using a high-performance cache-oriented compression algorithm modified to better suit our purpose, manages to further extend the lifetime of the memory system. In particular, it guarantees that at least half of the physical pages are in usable condition for 25% longer than ECP, which is slightly more than 5% more than a scheme that can correct 16 failures per block.

This paper is inspired on the structure of the field-oriented control by presenting an analytical and practical study of an adaptive nested controller for trajectory tracking control of a permanent magnet synchronous motor (PMSM) driving a single-link arm. The originality of the new approach relies in the use of adaptive control to compensate the electrical and mechanical dynamics and in the presentation of a rigorous closed-loop system stability analysis based on Lyapunov theory. It is worthwhile to notice that the new controller resembles the pure field-oriented control except for the adaptive terms. The new scheme is compared with other methodologies as with the classical nonadaptive field-oriented control algorithm and with an adaptive controller proposed in the literature. A better tracking accuracy is obtained with the proposed adaptive scheme.

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

Fractional band-pass filters are a promising area in the signal processing. They are especially attractive as a method for processing of biomedical signals, such as EEG, where large signal distortion is undesired. We present two structures of fractional band-pass filters: one as an analog of classical second-order filter, and one arising from parallel connection of two fractional low-pass filters. We discuss a method for filter implementation — Laguerre Impulse Response Approximation (LIRA) — along with sufficient conditions for when the filter can be realized with it. We then discuss methods of filter tuning, in particular we present some analytical results along with optimization algorithm for numerical tuning. Filters are implemented and tested with EEG signals. We discuss the results highlighting the possible limitations and potential for development.

The paper presents a simple circuit for the realization of two digital modulation schemes: BPSK and ASK simultaneously, with the advantage of high input impedance at the signal input nodes and use of grounded resistors. The new circuits are based on the use of extra-$X$ current conveyor. Detailed analysis is given and circuit verification is carried out through simulations with a supply voltage of $\pm 1.25$V and $0.25\mu$m CMOS parameters to support the proposed circuit. Nonideal study is also given. An extended application of the circuit in realizing precision half-wave and full-wave rectifiers is further proposed by incorporating a simple modification to the proposed topology. The new proposed CMOS compatible electronic circuits enrich the utility of extra-$X$ current conveyor for realizing diverse electronic functions.

This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9V voltage supply and 8$\mu$W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18$\mu$m TSMC CMOS technology show good performances for the designed circuit.

Power estimation is of great value to power-aware adaptation and power provisioning in computing platforms. Performance counter measurements are widely used as main input of the power estimation. However, the number of hardware counters that can be simultaneously measured is relatively small, and the number of OS-level counters is usually far from endurable. As a result, how to pick up the most significant counters becomes an important pre-step of performance counters based power consumption modeling. As the most important criteria of counter selection, correlation between counter measurement and power dissipation has been widely used for several decades, and thus correlation ranking becomes a typical technique for counter selection. However, few works discuss its accuracy and the question why it should be the general first priority. This paper investigates the weightiness of the correlation ranking in counter selection for power estimation. Through comparing correlation ranking with several popular feature selection approaches on tremendous workloads on single and multiple core platforms, we obtain that correlation ranking is not optimal on a large number of benchmarks. Therefore, it can be concluded that correlation ranking should not be generally considered as the first priority to select performance counters. This paper provides an indication for potential researchers to be aware of these issues when estimating power dissipation.

This paper presents a reconfigurable architecture for Network-on-Chip (NoC) design based on configuration switches. Reconfiguration is achieved by varying connection pattern between routers, depending on the currently running application. Mapping and reconfiguration strategies have been developed for the proposed architecture. In the mapping phase, cores in the combined application set are mapped to individual routers, minimizing the overall communication cost. In the second phase, for each application, configuration information for the switches (between the routers) are generated to optimize the communication cost further to suit the corresponding application. Exact methods, based on Integer Linear Programming (ILP), have been proposed for both the phases. Since ILP takes a large amount of CPU time, Particle Swarm Optimization (PSO)-based approaches have also been developed. The architecture and mapping strategies have been evaluated against benchmarks, considering communication cost, throughput, latency and network energy before and after reconfiguration. Significant improvements could be achieved via reconfiguration. Compared to the approaches reported in the literature, communication cost, throughput, latency and energy consumption values improve by 23.4%, 4%, 3% and 7%, respectively. These improvements come at a nominal increase in area overhead of 0.07%.

A constant voltage AC–DC converter based on the digital assistant technology is proposed in this paper, which has the advantage of high output precision. In this paper, a novel digital exponential wave generator is adopted in Constant Voltage (CV) mode to replace the normal triangle waveform to obtain a wider range of switching frequency, increasing the accuracy of output voltage under light load. The control chip is implemented based on NEC 1$\mu$m 5V/40V HVCMOS process, and a 5V/1.2A prototype has been built to verify the proposed control method. In PFM mode the deviation of output voltage is within $\pm 1.5$% and the load regulation is $\pm 0.92$%. Meanwhile, when the load jumps from light to heavy, the minimum output voltage could be maintained above 4.16V.

To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31$\mu$W, and the power loss of the entire converter is only 16.53$\mu$W.

As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for VLSI circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for CMOS devices. Because both the NBTI and leakage are dependent on input vector of the circuit, we present an input vector control (IVC) method based on an integer linear programming (ILP) approach. A novel NBTI and leakage reduction criterion function as well as an ILP formulation are presented to simultaneously minimize the delay degradation and leakage power. Our proposed ILP formulation can be generated adaptively for different circuits that can help the designers find the optimal input vector conveniently. In addition, the proposed method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed method.

Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over $GF(2^{163})$ and $GF(2^{233})$ using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions.

A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented in this paper. The PFD consists of two identical building blocks. Each PFD block generates UP or DOWN signal and consists of $p$- and $n$-precharge stages connected in cascade. The proposed PFD circuit has no feedback path and has zero dead-zone in the phase characteristic, what is important in low jitter applications. It also has minimal blind-zone (extended input detection range) close to the limit imposed by the used CMOS technology. The PFD is designed in 0.13$\mu$m BiCMOS technology and has 1.8V supply voltage. The simulation results of blind-zone values are within the range from $1^{\circ }$ for 1GHz up to $4^{\circ }$ for 8GHz. This circuit can be used in applications for high-frequency and low-power delay locked loop and phase locked loop circuits, effectively.

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18$\mu$m CMOS technology parameters under supply voltage of 0.9V are reported which show input and output voltage requirements of 40mV and 0.1V respectively, low THD of 1.2%, $R_{\mathrm{\text{in}}}$ of 496$\mathrm{\Omega }$, $R_{\mathrm{\text{out}}}$ of 1M$\mathrm{\Omega }$, $-$3dB bandwidth of 181MHz and power dissipation of 154$\mu$W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance.

The Road extraction from the remotely sensed imagery is highly realistic for the quick road updating in the Geographic Information System (GIS) data collection. The particle filter (PF) was earlier employed to track the road maps in satellite images. In our previous work, we have introduced an efficient Gauss–Hermite Kalman Filter with Locally Excitatory Globally Inhibitory Oscillator Networks (GHKF–LEGION)-based road extraction, even though it does not properly extract the road from the complex region. In order to recover the track of the road beyond obstacles, in this work, we proposed a novel hybrid multi-kernel partial least squares (PLS) with PF approach. Here, at first, we estimate the initial leader point of the road employing the K-means clustering technique. Subsequently, the PF traces a road till a stopping benchmark is satisfied. Thereafter, without finishing the process, the outcomes are furnished to the hybrid kernel PLS technique which attempts to locate the continuance of the road after several potential road blocks or to locate the entire feasible road branches which are on the other side of the road junction. The outcomes are offered for five satellite images. The experimental results show our proposed road tracking method is better compared to other existing works.

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-$\mu$m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200mV output swing for a pulse signal input at 1GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1GHz, validate the design.

This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99$\mu$s (200k$\mathrm{\Omega }$ to 204.8M$\mathrm{\Omega }$) and other four having conductance ranging from 195ns to 190$\mu$s (5.2k$\mathrm{\Omega }$ to 5.12M$\mathrm{\Omega }$). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process.

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6mW under a 0.8V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04GHz as the tuning voltage is varied from 0.8 to 0.0V. The phase noise is $-$118.3dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.36GHz and the corresponding figure-of-merit of the QVCO is $-$183.7dBc/Hz.

Feed-Forward Neural Networks (FFNNs), as one of the wide-spreading Artificial NNs, has been used to solve many practical problems such as classification of the sonar dataset. Improper selection of the training method, which is an important part of the design process, results in slow convergence rate, entrapment in local minima, and sensitivity to initial conditions. To overcome these issues, the recently proposed method known as “Particle Swarm Optimizer with Autonomous Groups (AGPSO)” has been used in this paper. It is known that the FNNs are very sensitive to the problem’s dimension, so clearly applying it to a dataset with large dimension results in poor performance. However, the combination of FNN and AGPSO solves this problem because of the ability of AGPSO in the optimization of high dimension problems. To evaluate the performance of the proposed classifier, it is applied to other datasets and the results are compared to the standard PSO, modified PSO (IPSO), Gravitational Search Algorithm (GSA) and Gray Wolf Optimizer (GWO). Simulation results show that the AGPSO classifier provides better performance in terms of convergence speed, entrapment in local minima and classification accuracy compared to the other algorithms.