Journal of Circuits, Systems and Computers

The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

This paper presents a novel Nyquist SAR-VCO ADC architecture. To improve the dynamic performance, a 4-phase counter is introduced to the proposed architecture. Thanks to the employed 4-phase counter, requirements on both the counting time error and the nonlinearity of the VCO gain are relaxed. In addition, rather than adopting the oversampling strategy to realize the noise-shaping, the proposed Nyquist architecture can quantize signals at as high as the Nyquist frequency. Hence, the signal bandwidth is broadened successfully. Beyond these, influences of nonideal effects (such as linearity of the VCO gain, mismatch between the differential VCO gains, counting time error and clock jitter) from practical circuit implementations and layout designs are theoretically analyzed and modeled. Behavioral simulations show that, at the near Nyquist input frequency and 10MS/s sampling rate, an SNDR of 61.43dB, an SFDR of 78.08dB and an ENOB of 9.91 bit are achieved, respectively.

Aiming at the efficient topology design of upper-layer network in hybrid application-specific wireless Network-on-Chip (NoC), we propose a new design method of power-interference collaborative optimization (PICO) after analyzing the potential factors of high power consumption and interference, and establishing relevant mathematical model. The design method is used for generating optimal irregular topology of ultralow power-interference using effective wireless link placement and channel assignment based on heuristic search algorithm under certain signal-to-interference plus noise ratio and strict resource constraints, such as the available number of wireless links and silicon area. In addition, the traffic balance between channels is carefully considered in the topology optimization. The theoretical calculation and cycle-accurate simulation results demonstrate that the resulting irregular topology generated by the co-optimization design method outperforms the conventional counterparts in terms of achievable throughput, power efficiency and bandwidth.

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 $n>8$ rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18$\mu$m @ 1.8V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

In this paper, a flux-controlled memristor with linear memductance is proposed. Compared with the memristor with piecewise linear memductance and the memristor with smooth continuous nonlinearity memductance which are widely used in the study of memristive chaotic system, the proposed memristor has simple mathematical model and is easy to implement. Multisim circuit simulation and breadboard experiment are realized, and the memristor can exhibit a pinched hysteresis loop in the voltage–current plane when driven by a periodic voltage. In addition, a new hyper-chaotic system is presented in this paper by adding the proposed memristor into the Lorenz system. The transient chaos and multiple attractors are observed in this memristive system. The dynamical behaviors of the proposed system are analyzed by equilibria, Lyapunov exponents, bifurcation diagram and phase portrait. Finally, an electronic circuit is designed to implement the hyper-chaotic memristive system.

A modified divide-by-2 regenerative frequency divider (RFD) is presented in this paper. The effects of modified active loads on the bandwidth of RFD are demonstrated and analyzed in detail by introducing the equivalent circuit using $\pi$ model. Using the transimpedance amplifier structure with resistive shunt–shunt feedback and shunt-peaked inductor as the active loads of the generative frequency divider, the loop bandwidth and the loop gain can be increased at higher frequencies to extend the bandwidth. Based on the theoretical analysis and design methodology, an RFD with improved active loads is designed and fabricated in 1$\mu$m GaAs heterojunction bipolar transistor technology with a total chip area of 0.83mm$\times$0.75mm. The measured phase noise at the divider output is less than $-$110dBc/Hz with 100kHz offset and is $-$127.6dBc/Hz with 1MHz offset. The operation frequency range is from 10 to 26GHz. The power consumption of the divider core is 166.44mW, and the frequency bandwidth is 16GHz at a supply voltage of $-$6V.

In this paper, a systematic and hierarchical synthesis methodology is presented for nonlinear analog synthesis to meet the essential requirement for system automation. Behavior of nonlinear system, represented by polynomial expression, has been studied by decomposing it into linear and nonlinear sub-expression. Such sub-expressions are realized with basic building block like multiplier, adder, quadratic, etc., each of which can be represented as a network of the current mode device, operational transconductance amplifier (OTA). Polynomial series is used to represent various important functions in signal processing applications. Few nonlinear functions with their OTA representation are discussed as the applications of polynomial series. The response of all the circuits are studied through SPICE simulation validating the proposed methodology.

A new method for reducing power consumption in finite state machines (FSMs) is proposed. Probabilistic description of the FSMs is the theoretical background of power-oriented state assignment. The algorithm of state assignment is based on a decomposition strategy of coding. This idea uses a binary tree in which nodes are created by sharing a finite state machine. The algorithm has been applied to the LGSynth91 benchmark and has also been compared to other approaches. The experiments showed that the proposed method leads to a reduction in power consumption compared to the state encoding algorithms that have already been developed. Reduction of the circuits’ area is also observed.

In this paper, a hybrid technique is proposed for controlling the $Z$-source inverter fed induction motor drive system. The hybrid technique is the combination of the gravitational search algorithm (GSA) and the support vector machine (SVM), which is utilized to improve the performance of the induction motor (IM). The novelty of the study is to control the $Z$-Source Inverter for improving the stability and performance of the IM drive system with the help of the proposed hybrid technique. Subsequently, the total harmonic distortion (THD) is decreased and the oscillation period of the stator current, torque and speed are eliminated. The inputs of the proposed technique are motor speed and reference speed. The output of the proposed system is reference quadrature axis current. Moreover, the PI controller is optimized for getting an optimal result to produce reference quadrature axis current. After that, the SVM is used to predict the control pulses of voltage source inverter. Here, the three-phase reference current is used to generate the accurate control pulses. In three-phase reference current, SVM is trained by the input motor quadrature axis current and the reference quadrature axis current with the associated target reference. The proposed technique is implemented in the MATLAB/simulink platform. The performance of the proposed method is determined and compared with the existing methods such as PSO-SVM and SVM methods.

Most existing stand-alone photovoltaic (PV) power systems employ pulse-width-modulated (PWM) DC–DC converters for maximum power point tracking (MPPT) and battery charging control. However, PWM converters experience high switching loss and high electromagnetic interference when operating at high frequency. Therefore, this paper presents an incremental conductance (INC)-based MPPT with constant voltage (CV) charging using LLC resonant converter for stand-alone solar streetlight system. INC MPPT maximizes the PV power generation while CV charging ensures good battery charging characteristics. Both the INC MPPT and CV charging are implemented in an algorithm using an Arduino Uno board. Detailed design procedure as well as extensive design considerations for a 100W prototype LLC resonant converter are presented. Experimental results show good MPPT performance under various environmental conditions such as sudden rise or sudden drop of incident irradiance. Furthermore, the system shows exceptional robustness in toggling between INC MPPT mode and CV charging mode depending on the environmental conditions. The converter displays excellent switching operation by achieving primary-side zero voltage switching and secondary-side zero current switching for the entire design range.

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54dB and 13.5mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

The pixel purity index (PPI) algorithm is one of the most popular endmember extraction algorithms employed in hyperspectral image unmixing, which is too time-consuming to obtain real-time analysis in remote sensing applications. The fast field programmable gate array (FPGA) implementation for computing the PPI is proposed in this reported work. The parallel strategy by skewers consumes lower I/O bandwidth and on-chip memory capacity, and the Xilinx Vivado high-level-synthesis (HLS) tool speeds up our architecture design and implementation. The overall design can be simple to implement, and makes the FPGA hardware appealing for on-board hyperspectral unmixing.

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has $\sim$91% smaller energy delay product (EDP) and $\sim$84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V V_DD.

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18$\mu$m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than $-10.0$dB over 2.5–11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present $n$ digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts.

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to $L$d$i$/d$t$. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times ($T_n$, parameters of the problem) with different values of current ($I_n$, other parameters of the problem). Basically, an ensemble of “$n$” number of transistors will be turned ON at time $t=T_n$ while it will pump the total current $I=I_n$. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

Feedback is an integral part of many analog circuits. This paper presents a method for the design of feedback networks for analog amplifiers based on Fixator–Norator Pair (FNP). The design process for required transfer function includes inserting proper FNPs to the equivalent small signal model of the target circuit, with norators lying along the feedback path, and helps to design the feedback network components. Care must be taken to ensure that the added feedback should not alter the original DC biasing of the circuit. A number of examples are worked out in this paper using the proposed method and the results are verified. The FNP approach gives a one-step solution for the design problems which otherwise require tedious analysis and calculations. Although the scope of this paper is limited to design of feedback for amplifiers, a skillful designer can extend the proposed method to other areas of analog circuits.